Patents by Inventor Kotaro Fujii

Kotaro Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956959
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
  • Publication number: 20240096795
    Abstract: A semiconductor storage device according to an embodiment includes a first wiring, a second wiring, a first insulating layer, a first insulator, and a conductor. The first insulating layer has a first portion, a second portion, and a third portion. The first portion is stacked on the first wiring. The second portion is stacked on the second wiring. The third portion is on the opposite side of the first wiring and the second wiring with respect to the first portion and the second portion.
    Type: Application
    Filed: March 13, 2023
    Publication date: March 21, 2024
    Applicant: Kioxia Corporation
    Inventor: Kotaro FUJII
  • Patent number: 11672117
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: June 6, 2023
    Assignee: Kioxia Corporation
    Inventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
  • Publication number: 20220302055
    Abstract: According to one or more embodiments, a semiconductor device includes a first substrate and a second substrate. The first substrate includes a first metal layer and a first insulating layer. The first insulating layer surrounds the first metal layer. The second substrate includes a second metal layer, a second insulating layer, and a first conducive body. The second metal layer is in contact with the first metal layer. The second insulating layer surrounds the second metal layer and is in contact with the first insulating layer. A part of the first conductive body is in the second metal layer and extends in a first direction toward the first metal layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: September 22, 2022
    Inventors: Kotaro FUJII, Shinya WATANABE
  • Publication number: 20220115684
    Abstract: A solid electrolyte having high electrical conductivity even in a low-temperature region is provided. A solid electrolyte containing a hexagonal perovskite-related compound, in which the compound is a compound represented by the following general formula (1), and an electrolyte layer and a battery using the solid electrolyte are disclosed. Ba7-?Nb(4?x-y)Mo(1+x)MyO(20+z) (1), in the formula (1), M is a cation of at least one element; a represents a Ba deficiency amount and represents a value of 0 or more and 0.5 or less, x represents a value of ?1.1 or more and 1.1 or less, y represents a value of 0 or more and 1.1 or less, and z represents an oxygen non-stoichiometry and represents a value of ?2.0 or more and 2.0 or less, provided that in the formula (1), |x|+y?0.01 is satisfied.
    Type: Application
    Filed: January 24, 2020
    Publication date: April 14, 2022
    Applicant: Tokyo Institute of Technology
    Inventors: Masatomo Yashima, Takafumi Tsujiguchi, Kotaro Fujii, Eiki Niwa, Yuichi Sakuda, Taito Murakami, Yuta Yasui, Yugo Kikuchi, Yuki Suzuki
  • Publication number: 20210280603
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
  • Patent number: 11088162
    Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 10, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Kotaro Fujii, Satoshi Nagashima, Yumi Nakajima
  • Patent number: 11049878
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
  • Patent number: 11018150
    Abstract: A semiconductor memory device includes a first electrode film, a second electrode film separated from the first electrode film in a first direction, a third electrode film separated from the second electrode film in the first direction, a fourth electrode film separated from the third electrode film in the first direction, and a first and a second semiconductor members extending in the first direction. The second electrode film includes a first conductive portion, an insulating portion, and a second conductive portion arranged along a second direction. The first semiconductor member pierces the first, third and fourth electrode films and the insulating portion of the second electrode film. The second semiconductor member pierces the first, third and fourth electrode films, and the first conductive portion or the second conductive portion of the second electrode film.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 25, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kotaro Fujii, Yasuhiro Uchiyama, Masaru Kito
  • Publication number: 20210126003
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.
    Type: Application
    Filed: January 7, 2021
    Publication date: April 29, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Kotaro FUJII, Jun FUJIKI, Shinya ARAI
  • Patent number: 10937803
    Abstract: According to one embodiment, a semiconductor storage device includes a stacked body, a first semiconductor layer extending in the stacked body, a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer, a second conductor layer disposed above the stacked body, a second semiconductor layer extending through the second conductor layer, a third conductor layer disposed between the second semiconductor layer and the second conductor layer, a first insulator layer disposed above the third conductor layer, and a second insulator layer including a first portion disposed between the second semiconductor layer and the third conductor layer and a second portion disposed between the second semiconductor layer and the first insulator layer. A diameter of the second insulator layer is larger in the second portion than in the first portion.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Kashima, Kohei Nyui, Kotaro Fujii, Hiroyuki Yamasaki
  • Patent number: 10923490
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: February 16, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
  • Publication number: 20200343264
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
  • Publication number: 20200273876
    Abstract: According to one embodiment, a semiconductor storage device includes a stacked body, a first semiconductor layer extending in the stacked body, a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer, a second conductor layer disposed above the stacked body, a second semiconductor layer extending through the second conductor layer, a third conductor layer disposed between the second semiconductor layer and the second conductor layer, a first insulator layer disposed above the third conductor layer, and a second insulator layer including a first portion disposed between the second semiconductor layer and the third conductor layer and a second portion disposed between the second semiconductor layer and the first insulator layer. A diameter of the second insulator layer is larger in the second portion than in the first portion.
    Type: Application
    Filed: August 2, 2019
    Publication date: August 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki KASHIMA, Kohei NYUI, Kotaro FUJII, Hiroyuki YAMASAKI
  • Patent number: 10756104
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
  • Publication number: 20200144278
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
  • Publication number: 20200075622
    Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.
    Type: Application
    Filed: February 25, 2019
    Publication date: March 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kotaro FUJII, Satoshi NAGASHIMA, Yumi NAKAJIMA
  • Patent number: 10566339
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 18, 2020
    Assignee: Toshiba Memory Coporation
    Inventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
  • Publication number: 20190296042
    Abstract: A method for manufacturing a semiconductor memory device includes forming a plurality of connection portions on a plurality of main body portions by filling a semiconductor material into a plurality of second through-holes, and after the forming of the plurality of connection portions, removing the third layer and a remaining portion of the second layer, the remaining portion of the second layer not being removed in the removing of the portion of the second layer.
    Type: Application
    Filed: September 11, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi NAKAKI, Kotaro FUJII
  • Publication number: 20190296040
    Abstract: A semiconductor device according to an embodiment includes first conductors, first pillars, a pillar column. Each of the first pillars is provided through the first conductors. The pillar column includes second pillars that are aligned in a first direction. Each of the second pillars is provided through the first conductors. The pillar column includes first and second columns of the second pillars. The first and second columns of the second pillars are aligned in a second direction that intersects the first direction. The first pillars are arranged on both sides in the second direction of each pillar column. The first conductors are provided continuously on both sides in the second direction of the second pillars that are included in each pillar column.
    Type: Application
    Filed: September 5, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kotaro FUJII, Masahisa SONODA, Masaru KITO, Satoshi NAGASHIMA, Shigeki KOBAYASHI