Abstract: A semiconductor memory device includes a first electrode film, a second electrode film separated from the first electrode film in a first direction, a third electrode film separated from the second electrode film in the first direction, a fourth electrode film separated from the third electrode film in the first direction, and a first and a second semiconductor members extending in the first direction. The second electrode film includes a first conductive portion, an insulating portion, and a second conductive portion arranged along a second direction. The first semiconductor member pierces the first, third and fourth electrode films and the insulating portion of the second electrode film. The second semiconductor member pierces the first, third and fourth electrode films, and the first conductive portion or the second conductive portion of the second electrode film.

Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.

Abstract: The memory string comprises: a first semiconductor layer; a stacked body in which a plurality of conductive layers and a plurality of interlayer insulating layers are stacked along a first direction above the first semiconductor layer; and a second semiconductor layer having a longitudinal direction along the first direction and provided above the first semiconductor layer. The memory insulating layer includes a charge accumulation layer between the second semiconductor layer and the plurality of the conductive layers. The core insulating layer has a longitudinal direction along the first direction, and is provided in the second semiconductor layer. The oxide film layer is provided between the core insulating layer and the second semiconductor layer.

Abstract: A semiconductor memory device according to one embodiment includes a stacked body and a semiconductor layer. The stacked body includes a plurality of control gate electrodes stacked above a substrate. The semiconductor layer extends in a first direction intersecting with the substrate and faces the plurality of control gate electrodes. The semiconductor memory device further includes a gate insulating layer disposed between the control gate electrodes and the semiconductor layer. The gate insulating layer includes zirconium oxide at a position facing the control gate electrodes.

Abstract: The memory string comprises: a first semiconductor layer; a stacked body in which a plurality of conductive layers and a plurality of interlayer insulating layers are stacked along a first direction above the first semiconductor layer; and a second semiconductor layer having a longitudinal direction along the first direction and provided above the first semiconductor layer. The memory insulating layer includes a charge accumulation layer between the second semiconductor layer and the plurality of the conductive layers. The core insulating layer has a longitudinal direction along the first direction, and is provided in the second semiconductor layer. The oxide film layer is provided between the core insulating layer and the second semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.

Abstract: According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first insulators, and arrays. The first interconnection is provided on a substrate via a first insulating film interposed. The first semiconductor region is provided on the first interconnection via a second insulating film. The stacked body is provided on the first semiconductor region. The columnar portion is provided in the stacked body. The first insulators are provided in the stacked body. The first insulators extend in the stacking direction and a first direction crossing the stacking direction. The arrays are provided in the first semiconductor region. The arrays each include second semiconductor regions. The second semiconductor regions are separated from each other. The second semiconductor regions are provided under the first insulators. The second semiconductor regions are electrically connected to the first interconnection.

Abstract: Perovskite related compound of the present invention have layered structures in which perovskite units and A-rare earth structure units are alternately arranged. The reduced cell parameters ar-cr and ?r-?r and the reduced cell volume Vr are within the following ranges: ar=6.05±0.6 ?, br=8.26±0.8 ?, cr=9.10±0.9 ?, ?r=103.4±10°, ?r=90±10°, ?r=90±10°, and Vr=442.37±67 ?3. At least one of the reduced cell parameters ar-cr can be m/n times as large as the aforementioned values, where m and n are independent natural numbers, the square roots of 2 or 3 or integral multiples thereof. Values of ar, br and cr can be replaced with one another, or values of ?r, ?r and ?r can be replaced with one another.

Abstract: According to one embodiment, the semiconductor film includes a first semiconductor part, a second semiconductor part, and a third semiconductor part. The first semiconductor part extends in the stacked body in a stacking direction of the stacked body. The second semiconductor part extends in the stacked body in the stacking direction and a first direction crossing the stacking direction. The third semiconductor part extends in the underlayer in a second direction connecting the first semiconductor part and the second semiconductor part. The first semiconductor part, the second semiconductor part and the third semiconductor part are made of a same material and are continuous with each other. The first metal layer is in contact with a side surface of the second semiconductor part.

Abstract: A semiconductor device includes a base body, an insulating layer, first contacts and a first wiring. The insulating layer is disposed above the base body. The first contacts are disposed in the insulating layer. The first contacts are in contact with the base body. The first wiring is disposed around the first contacts. The first wiring has a lower height than the first contacts have. The first wiring includes convex portions in a part of a bottom portion thereof.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes semiconductor regions, an element isolation region, control gate electrodes, a floating gate layer, a first insulating film, a second insulating film, a select gate electrode, and a contact electrode. The element isolation region is provided between the semiconductor regions. The control gate electrodes are provided on the semiconductor regions. The floating gate layer is provided in a position where the semiconductor regions and the control gate electrodes cross. The first insulating film is provided between the floating gate layer and the semiconductor regions. The second insulating film is provided between the floating gate layer and the control gate electrodes. The select gate electrode is provided on the semiconductor regions. The contact electrode is disposed on an opposite side of the select gate electrode from the control gate electrodes, and is in contact with one of the semiconductor regions.

Abstract: A semiconductor device includes memory cell units, each including memory cell transistors, a first transistor at a first end of the memory cell transistors, and a second transistor at a second end of the memory cell transistors. The memory cell units are arranged so that adjacent memory cell units have first transistors thereof facing each other or second transistors thereof facing each other, and so that a distance between the first transistors of the adjacent memory cell units is larger than a distance between the second transistors of the adjacent memory cell units. The semiconductor device further includes a first silicon nitride layer covering a first diffusion layer of the first transistors, a second silicon nitride layer covering a second diffusion layer of the second transistors. A thickness of the second silicon nitride layer is smaller than a thickness of the first silicon nitride layer.

Abstract: According to one embodiment, a nonvolatile memory device includes a first function layer. The first function layer includes a first electrode layer, a second electrode layer, and a variable resistance layer. The second electrode layer is opposed to the first electrode layer. The variable resistance layer is provided between the first electrode layer and the second electrode layer. Resistance state of the variable resistance layer is variable. The first function layer includes a first intermediate layer. The first intermediate layer is provided between the first electrode layer and the variable resistance layer. The first intermediate layer contacts the first electrode layer and the variable resistance layer.