Patents by Inventor Kotoku Sato
Kotoku Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090010080Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: August 29, 2008Publication date: January 8, 2009Inventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20080025127Abstract: To perform mask control of data signals without increasing the number of external terminals even when the number of bits in a data mask signal is large, an address input circuit sequentially receives a first address signal, a second address signal, and a first data mask signal supplied to an address terminal in synchronization with transition edges of a clock signal. Namely, the first data mask signal is supplied to the address terminal at a different timing from timing at which the first and second address signals are received. The first address signal, second address signal, and first data mask signal are output, for example, from a controller accessing a semiconductor memory. A data input/output circuit inputs/outputs data via a data terminal and masks at least either of write data to memory cells and read data from the memory cells in accordance with logic of the first data mask signal.Type: ApplicationFiled: February 13, 2007Publication date: January 31, 2008Inventors: Tatsuya Kanda, Kotoku Sato
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Patent number: 7239569Abstract: A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.Type: GrantFiled: July 19, 2006Date of Patent: July 3, 2007Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Kotoku Sato
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Publication number: 20070014178Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: September 6, 2006Publication date: January 18, 2007Inventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20070002664Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: September 6, 2006Publication date: January 4, 2007Inventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20060256639Abstract: A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.Type: ApplicationFiled: July 19, 2006Publication date: November 16, 2006Inventors: Shinya Fujioka, Kotoku Sato
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Patent number: 7102949Abstract: A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.Type: GrantFiled: December 30, 2004Date of Patent: September 5, 2006Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Kotoku Sato
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Patent number: 7057959Abstract: A method for controlling a semiconductor memory in which a mode register can be set in a burst mode. To set an operation mode in the burst mode, the semiconductor memory is changed first from the burst mode, through a power-down mode, to a standby mode of non-burst mode. Then the semiconductor memory is changed to a mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.Type: GrantFiled: December 2, 2004Date of Patent: June 6, 2006Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Shinichi Yamada, Kotoku Sato, Jun Ohno
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Publication number: 20050262369Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: ApplicationFiled: July 27, 2005Publication date: November 24, 2005Inventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
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Publication number: 20050259492Abstract: A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.Type: ApplicationFiled: December 30, 2004Publication date: November 24, 2005Inventors: Shinya Fujioka, Kotoku Sato
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Patent number: 6961830Abstract: A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.Type: GrantFiled: December 24, 2002Date of Patent: November 1, 2005Assignee: Fujitsu LimitedInventors: Hitoshi Ikeda, Yasuharu Sato, Takaaki Suzuki, Toshiya Uchida, Kotoku Sato
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Publication number: 20050185493Abstract: A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.Type: ApplicationFiled: April 25, 2005Publication date: August 25, 2005Inventors: Shinya Fujioka, Kotoku Sato, Hitoshi Ikeda, Yoshiaki Okuyama, Jun Ohno
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Publication number: 20050094480Abstract: A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.Type: ApplicationFiled: December 2, 2004Publication date: May 5, 2005Inventors: Shinya Fujioka, Shinichi Yamada, Kotoku Sato, Jun Ohno
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Patent number: 6842391Abstract: A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.Type: GrantFiled: September 5, 2003Date of Patent: January 11, 2005Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Shinichi Yamada, Kotoku Sato, Jun Ohno
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Publication number: 20040184325Abstract: A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.Type: ApplicationFiled: September 5, 2003Publication date: September 23, 2004Applicant: Fujitsu LimitedInventors: Shinya Fujioka, Shinichi Yamada, Kotoku Sato, Jun Ohno
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Patent number: 6735141Abstract: A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.Type: GrantFiled: July 31, 2001Date of Patent: May 11, 2004Assignee: Fujitsu LimitedInventors: Hitoshi Ikeda, Akihiro Funyu, Shinya Fujioka, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato
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Patent number: 6724675Abstract: A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.Type: GrantFiled: January 29, 2003Date of Patent: April 20, 2004Assignee: Fujitsu LimitedInventors: Akihiro Funyu, Shinya Fujioka, Hitoshi Ikeda, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato, Yasurou Matsuzaki
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Patent number: 6629224Abstract: Signals supplied to predetermined terminals are accepted as commands at a plurality of times, the number of operating modes is sequentially narrowed down based on the command each time and an internal circuit is controlled according to the narrowed operating modes. Since the information necessary for determining an operating mode is accepted at a plurality of times, the number of terminals necessary for inputting commands can be reduced. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be required so that the chip size can be reduced. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size. The command controlling circuit with a plurality of accepting circuits is comprised. Each of the accepting circuits respectively accepts signals, supplied at a plurality of times, each time.Type: GrantFiled: May 1, 2000Date of Patent: September 30, 2003Assignee: Fujitsu LimitedInventors: Takaaki Suzuki, Toshiya Uchida, Kotoku Sato, Yoshimasa Yagishita
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Publication number: 20030135707Abstract: A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.Type: ApplicationFiled: December 24, 2002Publication date: July 17, 2003Applicant: FUJITSU LIMITEDInventors: Hitoshi Ikeda, Yasuharu Sato, Takaaki Suzuki, Toshiya Uchida, Kotoku Sato
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Patent number: 6584032Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.Type: GrantFiled: September 12, 2001Date of Patent: June 24, 2003Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato