Patents by Inventor Kouichi Itoh
Kouichi Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240045983Abstract: A verification method for a computer to execute a process includes receiving a verification request for a first document created by a first person together with first information that identifies a reliability of document creation by the first person, the first information being generated based on evaluation information on documents created by the first person; in a case where the verification request is received, generating second information depending on the reliability of the document creation by the first person based on the received first information; and outputting a verification result of the first document, the result containing the generated second information.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Applicant: FUJITSU LIMITEDInventors: Kazuya Uno, Kouichi Itoh
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Publication number: 20230205933Abstract: A verification method implemented by a computer, the verification method including: acquiring a transmission source of a transmitted target document and first signature pattern information that represents a feature of one or a plurality of signatures regarding the target document; extracting second signature pattern information associated with the acquired transmission source of the target document from a storage unit that stores signature pattern information that represents a feature of one or a plurality of signatures regarding a document acquired in the past in association with a transmission source of the document; and verifying reliability of the target document, based on a result of comparing the acquired first signature pattern information and the extracted second signature pattern information.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Applicant: FUJITSU LIMITEDInventors: Yoshinori KATAYAMA, Koichi YASAKI, Kouichi ITOH, Dai YAMAMOTO, Kazuaki NIMURA
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Publication number: 20230208650Abstract: An information processing method is executed by a computer, the information processing method includes: obtaining a first evaluation value for an evaluation item related to reliability corresponding to a combined signature that is obtained by aggregating therein a plurality of signatures, and a second evaluation value for an evaluation item related to reliability corresponding to any one signature of the plurality of signatures; and executing, when the obtained first evaluation value and the obtained second evaluation value differ from each other, control of changing the second evaluation value using the first evaluation value or changing the first evaluation value using the second evaluation value, according to a hierarchical relation between the combined signature and the any one signature, based on a type of the evaluation item.Type: ApplicationFiled: February 24, 2023Publication date: June 29, 2023Applicant: FUJITSU LIMITEDInventors: Hidenobu Oguri, Kouichi Itoh
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Publication number: 20180365769Abstract: An information processing apparatus is configured to, regarding each of a plurality of objects, acquire a record including location information of an object, speed information of the object, time information that represents a time at which the location information and the speed information have been acquired, and identification information of the object, identify a first record including the identification information corresponding to a target object, the time information corresponding to a target time section, and the location information corresponding to a target space section, identify a plurality of second records each of which includes the time information corresponding to the target time section and the location information corresponding to the target space section, identify a degree of risk of the target object based on difference between a representative value of the speed information included in the plurality of second records and the speed information included in the first record.Type: ApplicationFiled: May 31, 2018Publication date: December 20, 2018Applicant: FUJITSU LIMITEDInventors: Yuji Yamaoka, Hiroshi OGASAWARA, Yuji KOTERA, Takahiro Akutsu, Kouichi ITOH
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Patent number: 10025784Abstract: A determination apparatus has a feature extraction unit and a similarity determination unit. The feature extraction unit counts a number of appearances of each keyword included in a piece of document information and deletes any arrangement including a keyword having the number of appearances less than a threshold under a condition where a number of types of keyword arrangements included in a certain range of the piece of document information is equal to or greater than a certain number and extracts, as features, a plurality of keyword arrangements from the piece of document information. The similarity determination unit determines a similarity between the different pieces of document information by comparing the features extracted from pieces of document information different from each other.Type: GrantFiled: December 14, 2015Date of Patent: July 17, 2018Assignee: FUJITSU LIMITEDInventors: Fumihiko Kozakura, Kouichi Itoh
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Patent number: 9760616Abstract: A computer is disclosed that performs an electronic mail creation process. The computer creates an electronic mail by referring to a storage part in which received electronic mails are stored, using at least one electronic mail of the received electronic mails stored in the storage part, the at least one electronic mail selected based on a criteria being set beforehand, and changing at least one of header information and a body text of the at least one electronic mail.Type: GrantFiled: September 5, 2014Date of Patent: September 12, 2017Assignee: FUJITSU LIMITEDInventors: Takeaki Terada, Satoru Torii, Masanobu Morinaga, Ikuya Morikawa, Kouichi Itoh, Hiroshi Tsuda
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Patent number: 9749135Abstract: From the least significant bit of the current secret key, k bits are retrieved, obtaining a binary window sequence. A binary bit string of concatenation of the random number to the more significant bits of the window sequence is obtained if the most significant bit of the window sequence is 0, subtracting a bit string from the current secret key to obtain a new secret key, or the bit string of a complement of the base number for the window sequence in binary system is calculated if the most significant bit of the window sequence is 1, obtaining a bit string by adding a minus sign to a bit string obtained by concatenating the random number to the more significant bits of the bit string, subtracting the bit string from the current secret key to obtain a new secret key.Type: GrantFiled: June 23, 2016Date of Patent: August 29, 2017Assignee: FUJITSU LIMITEDInventors: Jun Yajima, Kouichi Itoh, Masahiko Takenaka, Dai Yamamoto
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Publication number: 20170109535Abstract: An investigation apparatus according to an embodiment includes a processor that executes a process including: analyzing uniqueness of a plurality of values included in an attribute for each attribute of a table; reducing a plurality of values included in an attribute of which the analyzed uniqueness is lower than a predetermined value by a predetermined ratio with respect to an investigation original table and outputting a feature of the investigation original table; reducing a plurality of values included in an attribute of which the analyzed uniqueness is higher than a predetermined value by a predetermined ratio with respect to an investigation target table and outputting a feature of the investigation target table; and investigating similarity of the investigation target table to the investigation original table by comparing the feature of the investigation original table with the feature of the investigation target table.Type: ApplicationFiled: September 14, 2016Publication date: April 20, 2017Applicant: FUJITSU LIMITEDInventors: Fumihiko Kozakura, Kouichi ITOH
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Publication number: 20170048067Abstract: From the least significant bit of the current secret key, k bits are retrieved, obtaining a binary window sequence. A binary bit string of concatenation of the random number to the more significant bits of the window sequence is obtained if the most significant bit of the window sequence is 0, subtracting a bit string from the current secret key to obtain a new secret key, or the bit string of a complement of the base number for the window sequence in binary system is calculated if the most significant bit of the window sequence is 1, obtaining a bit string by adding a minus sign to a bit string obtained by concatenating the random number to the more significant bits of the bit string, subtracting the bit string from the current secret key to obtain a new secret key.Type: ApplicationFiled: June 23, 2016Publication date: February 16, 2017Applicant: FUJITSU LIMITEDInventors: Jun YAJIMA, Kouichi ITOH, Masahiko TAKENAKA, Dai YAMAMOTO
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Publication number: 20160248585Abstract: A cryptographic apparatus and method is provided with which the circuit scale does not become large, even if a circuit that makes exposure of the secret key difficult by using Differential Power Analysis is equipped. First key data (dQ) representing a quotient obtained by exponentiating, with respect to respect prime data (pi), using respective random number setting data representing exponents (rpi) corresponding to respective prime data, and then obtaining multiplication data by multiplying the respective exponentiated data, and then dividing secret key data (d) by the multiplication data, and second key data (dR) representing a reminder obtained by dividing the secret key data by the multiplication data are stored in a storing unit in advance, and using the first key data and the second key data, a decryption process using RSA or ECC having a countermeasure against Differential Power Analysis (DPA) is performed.Type: ApplicationFiled: April 23, 2014Publication date: August 25, 2016Applicant: FUJITSU LIMITEDInventors: Jun Yajima, Kouichi ITOH
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Patent number: 9401805Abstract: k bits from the least significant bit of the current secret key are retrieved, obtaining a binary window sequence. A binary bit string of concatenation of the random number to the more significant bits of the window sequence is obtained if the most significant bit of the window sequence is 0, subtracting a bit string from the current secret key to obtain a new secret key, or the bit string of a complement of the base number for the window sequence in binary system is calculated if the most significant bit of the window sequence is 1, obtaining a bit string by adding a minus sign to a bit string obtained by concatenating the random number to the more significant bits of the bit string, subtracting the bit string from the current secret key to obtain a new secret key.Type: GrantFiled: June 26, 2013Date of Patent: July 26, 2016Assignee: FUJITSU LIMITEDInventors: Jun Yajima, Kouichi Itoh, Masahiko Takenaka, Dai Yamamoto
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Publication number: 20160210339Abstract: A determination apparatus has a feature extraction unit and a similarity determination unit. The feature extraction unit counts a number of appearances of each keyword included in a piece of document information and deletes any arrangement including a keyword having the number of appearances less than a threshold under a condition where a number of types of keyword arrangements included in a certain range of the piece of document information is equal to or greater than a certain number and extracts, as features, a plurality of keyword arrangements from the piece of document information. The similarity determination unit determines a similarity between the different pieces of document information by comparing the features extracted from pieces of document information different from each other.Type: ApplicationFiled: December 14, 2015Publication date: July 21, 2016Inventors: Fumihiko Kozakura, Kouichi Itoh
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Patent number: 9330270Abstract: An encryption processing device includes a memory configured to store a common key, and a processor configured to generate a random number which is an integer, to perform a bit transposition on the common key, the bit transposition being determined at least by the random number, to transmit the random number to another encryption processing device and to receive a response from the other encryption processing device, the response obtained by encryption using a common key stored in the other encryption processing device and a second randomized key generated by performing the bit transposition determined by the random number; and to authenticate the other encryption processing device either by comparing the response with the random number by decrypting the response with the common key, or by comparing the random number with the response by encrypting the random number with the common key.Type: GrantFiled: January 22, 2014Date of Patent: May 3, 2016Assignee: FUJITSU LIMITEDInventors: Takao Ochiai, Kouichi Itoh, Dai Yamamoto, Kazuyoshi Furukawa, Masahiko Takenaka
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Patent number: 9166800Abstract: A method is disclosed for authenticating, by a processor that controls a parent device, a child device includes: authenticating the child device by making a comparison between a value obtained by operating, for a first response value, a third transform function, which is decided based on a number of a difference between the value set in an authentication chip of the parent device and the value set in an authentication chip of the child device, and the second response value, wherein a first and a second response values are obtained by operating a first and a second transform functions for output values generated by operating an encryption function for performing encryption for secret keys in authentication chips of the parent device and the child device, respectively.Type: GrantFiled: September 6, 2013Date of Patent: October 20, 2015Assignee: FUJITSU LIMITEDInventors: Kouichi Itoh, Masahiko Takenaka
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Patent number: 9130745Abstract: A constant multiplier inputs a base and a modulo n, performs modular exponentiation modulo n with a prescribed constant as the exponent and with base a, and outputs the result of this calculation as base b. A personal key converter inputs a personal key d and calculates a personal key d? as the quotient when d is divided by the prescribed constant. A correction key generator generates a correction key d? as the remainder of the aforementioned division. A first modular exponentiation unit performs modular exponentiation base b with d? as the exponent. A second modular exponentiation unit performs modular exponentiation base a with d? as the exponent, and outputs a correction value. A correction calculation unit multiplies the outputs of the first and second modular exponentiation units and outputs the result as the encryption processing result.Type: GrantFiled: June 26, 2013Date of Patent: September 8, 2015Assignee: Fujitsu LimitedInventors: Kouichi Itoh, Dai Yamamoto, Masahiko Takenaka
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Patent number: 9021001Abstract: The generation of individual-specific information having a good reliability and uniqueness is made possible with a little circuit scale. For this purpose, in an individual-specific information generation apparatus, a plurality of digital circuits are in the same circuit configuration. Each of the digital circuits outputs a fixed or a random number output value individually without their output with respect to a certain input being determined unambiguously among the digital circuits. In each of the digital circuit, an order is defined in advance. A random number judgment unit judges whether the output value is a random value or fixed, for each of the plurality of digital circuits. An individual-specific information generation unit generates the individual-specific information based on information of the order defined in the digital circuit judged by the random number judgment unit as having a fixed output value among the plurality of digital circuits and the output value.Type: GrantFiled: December 27, 2012Date of Patent: April 28, 2015Assignee: Fujitsu LimitedInventors: Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh
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Patent number: 9015218Abstract: A random number generator includes an exclusive-OR circuit, a random number determiner, and a random number generation instruction inhibitor. The exclusive-OR circuit obtains an exclusive-OR of outputs from a number of digital circuits. The random number determiner determines whether or not an output generated according to an instruction to generate random numbers is a random number for each of the digital circuits. The random number generation instruction inhibitor inhibits an instruction to generate random numbers to be provided to the digital circuits whose output generated according to the instruction is determined to be not a random number by the random number determiner.Type: GrantFiled: September 25, 2012Date of Patent: April 21, 2015Assignee: Fujitsu LimitedInventors: Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka
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Publication number: 20150081722Abstract: A computer is disclosed that performs an electronic mail creation process. The computer creates an electronic mail by referring to a storage part in which received electronic mails are stored, using at least one electronic mail of the received electronic mails stored in the storage part, the at least one electronic mail selected based on a criteria being set beforehand, and changing at least one of header information and a body text of the at least one electronic mail.Type: ApplicationFiled: September 5, 2014Publication date: March 19, 2015Inventors: Takeaki Terada, Satoru Torii, Masanobu Morinaga, Ikuya Morikawa, Kouichi ITOH, Hiroshi Tsuda
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Patent number: 8891759Abstract: A cryptographic processing device includes a private key storage unit which stores a private key d for elliptic curve cryptography, a random number generation unit which generates a b-bit random value s, and a processing unit. A bit string D is the private key d or a bit string obtained by modifying the private key d in such a way that a value of a most significant bit is 0, and a relation u=mk+b holds true for a length u of the bit string D, a window size k, and a positive integer m. The processing unit determines a signed k-bit window value w[i] corresponding to each i where 0?i?(m?1), a signed b-bit random value s[i] corresponding to each i, and a correction value g. The processing unit determines the above values under a certain constraint condition, while determining each random value s[i] to be +s or ?s.Type: GrantFiled: September 28, 2012Date of Patent: November 18, 2014Assignee: Fujitsu LimitedInventors: Kouichi Itoh, Dai Yamamoto, Masahiko Takenaka
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Patent number: 8817973Abstract: Based on an encrypting method for performing an exponential remainder calculation y=ad (mod n) from an u-bit exponent d=(du-1, . . . , d0)2, input data a, and a modulo n, calculating a?=a2(mod n) is performed first. Next, calculating y=(a?)f(mod n) is performed on f=(du-1, du-2, . . . , d1)2. Then, when d0=1, calculating y=y×a (mod n) is performed. Then, outputting y=ad (mod n) is performed. In the first step, although an attacker inputs data including a minus value such as a=?1 and a=s, ?s, etc., only plus values can be constantly generated in multiplication and squaring. Therefore, the method makes it hard to estimate a secret key using power analyzing attacks such as the SPA and the DPA, thereby realizing an encryption processor having high tamper-resistance.Type: GrantFiled: September 24, 2010Date of Patent: August 26, 2014Assignee: Fujitsu LimitedInventor: Kouichi Itoh