Patents by Inventor Kouichi Itoh

Kouichi Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110075836
    Abstract: An apparatus includes a data storage to store a window table storing a table value with an index value mapped to the table value, the index value having same number of bits as a window width, the table value being a sum of a basic table value and a non-zero table correction value, the basic table value being obtained by multiplying a point G on an elliptic curve. An arithmetic processor generates the index value by reading from a scalar value at a bit position assigned to each bit of the window with the window being shifted, reads the table value from the window table according to the index value, and performs a doubling operation and an addition operation using the read table value. A corrector performs a correction on arithmetic results with a specific correction value responsive to the table correction value.
    Type: Application
    Filed: September 27, 2010
    Publication date: March 31, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Dai YAMAMOTO, Kouichi Itoh
  • Publication number: 20110013770
    Abstract: Based on an encrypting method for performing an exponential remainder calculation y=ad (mod n) from an u-bit exponent d=(du?1, . . . , d0)2, input data a, and a modulo n, calculating a?=a2(mod n) is performed first. Next, calculating y=(a?)f(mod n) is performed on f=(du?1, du?2, . . . , d1)2. Then, when d0=1, calculating y=y×a (mod n) is performed. Then, outputting y=ad (mod n) is performed. In the first step, although an attacker inputs data including a minus value such as a=?1 and a=s, ?s, etc., only plus values can be constantly generated in multiplication and squaring. Therefore, the method makes it hard to estimate a secret key using power analyzing attacks such as the SPA and the DPA, thereby realizing an encryption processor having high tamper-resistance.
    Type: Application
    Filed: September 24, 2010
    Publication date: January 20, 2011
    Applicant: FUJITSU LIMITED
    Inventor: KOUICHI ITOH
  • Publication number: 20110013769
    Abstract: A common key block encryption apparatus for performing a nonlinear transformation with a multiplication executed in a binary field or a composite field includes a computing unit to execute a computation other than the nonlinear transformation with fixed value masked input data obtained by XORing input data with a fixed mask value, an XOR operation circuit to transform all input data into fixed value masked input data by XORing the input data with a fixed mask value and to transform the data into random value masked input data by XORing the input data with a random mask value in the multiplication, a multiplier to execute a multiplication based on the random value masked input data output from the XOR operation circuit, and a random value mask-to-fixed mask value transformation circuit to again transform the random value masked output data into fixed value masked output data and to output the data.
    Type: Application
    Filed: September 23, 2010
    Publication date: January 20, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Kouichi ITOH, Souichi OKADA, Masahiko TAKENAKA
  • Publication number: 20110007894
    Abstract: 401 stores, in 302, key d? obtained by subtracting random number 2r held in 201 from key d held in 105. When an operation starts, the values “?C” and “?C2” are calculated respectively, and the resultant values are stored in a multiplication table memory 205 together with value “C”. In a first operation cycle, 107 selects and outputs an intermediate value 108 held in an in-operation data register 103, and thereby makes a modular-multiplication operation circuit 104 perform squaring. In the second operation cycle, 107 selects and outputs one of three values held in 205 in accordance with the combination of key bit value d?i and random number bit value ri, and thereby makes the modular-multiplication operation circuit 104 perform multiplication. Thereby, a cryptographic processing device that requires a short operation time period, small circuit scale, and has sufficient security can be realized.
    Type: Application
    Filed: September 20, 2010
    Publication date: January 13, 2011
    Applicant: Fujitsu Limited
    Inventors: Masahiko TAKENAKA, Kouichi Itoh
  • Publication number: 20100278332
    Abstract: In a MISTY1 FI function, an exclusive OR to which a round key KIij2 is inputted is arranged between an exclusive OR arranged on a 9-bit critical path in a first MISTY structure and a zero-extend conversion connected to the branching point of a 7-bit right system data path. Then, a 9-bit round key KIij1 is truncate-converted to seven bits, the exclusive OR of the seven bits and the round key KIij1 is calculated by an exclusive OR and the calculation result is inputted to an exclusive OR arranged on the right system data path in the second stage MISTY structure.
    Type: Application
    Filed: July 12, 2010
    Publication date: November 4, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Dai YAMAMOTO, Jun Yajima, Kouichi Itoh
  • Publication number: 20100278340
    Abstract: When processing a data conversion function of a MISTY structure, such as the FO function of MISTY1, the logical calculation result t3 of the exclusive OR 614 of the process result of the FI function 602 of the MISTY structure in the second stage and a logical calculation result t1 of an exclusive OR 612 of the MISTY structure in the first stage is not stored in a register. The logical calculation result t3 and the logical calculation result of respective exclusive OR 642 and 643 are subject to a direct exclusive OR with the respective exclusive OR 642 and 643.
    Type: Application
    Filed: July 12, 2010
    Publication date: November 4, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Jun YAJIMA, Dai YAMAMOTO, Kouichi ITOH
  • Publication number: 20100232601
    Abstract: An apparatus for executing cryptographic calculation on the basis of an elliptic point on an elliptic curve includes: a memory for storing a first value including a plurality of digits; and a processor for executing a process including: obtaining a second value representing a point on the elliptic curve; calculating output values by using a predetermined equation, each digit of the first value, and the second value; determining whether at least one of the second value and the output values indicates a point of infinity; terminating the calculation when at least one of the second value and the output values indicates the point at infinity; and completing calculation when both the second value and the output values do not indicate the point at infinity, so as to obtain a result of the cryptographic calculation.
    Type: Application
    Filed: January 15, 2010
    Publication date: September 16, 2010
    Applicant: Fujitsu Limited
    Inventors: Kouichi ITOH, Dai Yamamoto, Tetsuya Izu, Masahiko Takenaka, Kazuyoshi Furukawa
  • Publication number: 20100232603
    Abstract: A decryption processor for calculating a plaintext through decryption of a ciphertext c includes, a first part that calculates m?p through modular exponentiation modulo a first prime number p wherein an exponent is a shifted value of d (mod (p?1)), and a base is a value of c (mod p); a second modular exponentiation part that calculates m?q through modular exponentiation modulo a second prime number q, wherein an exponent is a value of d (mod (q?1)) and a base is a value of c (mod q); a composition part that calculates ms through calculation of ((u×(m?q?m?p) (mod q))×p+m?p by using the values m?p and m?q and a private key u corresponding to p?1 (mod q); and a shift release part that calculates the plaintext m through calculation of ms×(cs (mod n)) (mod n) by using the value ms.
    Type: Application
    Filed: January 19, 2010
    Publication date: September 16, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Kouichi Itoh
  • Patent number: 7792893
    Abstract: A method for calculating a conversion parameter of the Montgomery modular multiplication to improve the efficiency of software installation, comprising a first step for calculating H0=2v×R (mod n) (where v is an integer, v?1, and (m×k)/v is an integer), a second step for calculating Hp=2v×2^p×R (mod n) from H0=2v×R (mod n) by repeating Hi=REDC(Hi?1, Hi?1)n with respect to i=1, 2, . . . , p (where p represents an integer satisfying the condition 2p?(m×k)/v>2p?1, REDC represents the Montgomery modular multiplication REDC(a, b)n=a×b×R?1 (mod n), and x^i represents exponential computation xi); and a third step for calculating Hp=R2 (mod n) by calculating Hp=REDC(Hp, g)n with respect to Hp obtained in the second step when 2p>(m×k)/v (where g=2k×E(p,m,k), E(p, m, k)=2×m?(v×2p)/k) and finally outputting Hp as R2 (mod n).
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: September 7, 2010
    Assignee: Fujitsu Limited
    Inventors: Kouichi Itoh, Masahiko Takenaka, Naoya Torii
  • Publication number: 20100183144
    Abstract: A cipher processing apparatus for arithmetic operations of an FO function and an FL function comprising: an FL function operating unit for generating a 2N-bit output based on a first extension key; a partial function operating unit for generating an N-bit output based on second and third extension keys; an N-bit intermediate register for storing an output of the partial operating unit; a 2N-bit first data register for storing data based on the output of the FL function operating unit; and a controller for making the partial function operating unit perform six cycles, inputting an output of the intermediate register to the FL function operating unit, and storing the data based on the output of the FL function operating unit in the first data register, in a first case in which the FL function uses a result of an arithmetic operation of the FO function.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 22, 2010
    Applicant: Fujitsu Limited
    Inventors: Dai Yamamoto, Kouichi Itoh, Jun Yajima
  • Publication number: 20100183143
    Abstract: A cryptographic processing apparatus for performing arithmetic operation on an FL function and an FL?1 function in a cryptographic process includes a first arithmetic gate is configured to receive a first input bit string and a first extended key bit string, a first XOR gate configured to receive an output of the first arithmetic gate and a second input bit string, a second arithmetic gate configured to receive an output of the first XOR gate and a second extended key bit string, a second XOR gate configured to receive an output of the second arithmetic gate and the first input bit string, a third arithmetic gate configured to receive an output of the second XOR gate and the first extended key bit string, and a third XOR gate configured to receive an output of the third arithmetic gate and an output of the first XOR gate.
    Type: Application
    Filed: November 4, 2009
    Publication date: July 22, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Dai YAMAMOTO, Kouichi Itoh
  • Publication number: 20100031055
    Abstract: A cryptographic processing device, comprising: a storage unit; initial setting unit for setting a value to be stored in the storage unit; Montgomery modular multiplication operation unit for performing a Montgomery modular multiplication operation plural times for a value set by the initial setting unit; and fault attack detection unit for determining whether or not a fault attack occurred for each of at least some parts of the Montgomery modular multiplication operations performed plural times.
    Type: Application
    Filed: September 15, 2009
    Publication date: February 4, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Kazuyoshi Furukawa, Kouichi Itoh, Masahiko Takenaka
  • Patent number: 7639808
    Abstract: An elliptic curve cryptosystem apparatus performing an elliptic curve cryptosystem process has a coordinate transforming unit for transforming coordinates (X:Y:Z) on a point P on an elliptic curve over a finite field GF(p^m) to coordinates (r1×(X?s1):r2×(Y?s2):r3×(Z?s3)) (where, p is a prime number, m is an integer not less than 1, r1, r2 and r3 are integers not less than 1 and not larger than (p?1), s1, s2 and s3 are integer not less than 0 and not larger than (p?1), and a code “^” represents power), and a scalar multiplication operating unit for performing scalar multiplication on the point on the elliptic curve transformed by the coordinate transforming unit, wherein at least one of the parameters s1, s2 and s3 has a value other than 0. The apparatus can perform the scalar multiplication in the elliptic curve cryptosystem, with resistance to side channel attacks.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: December 29, 2009
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Izu, Kouichi Itoh, Masahiko Takenaka, Naoya Torii
  • Patent number: 7578341
    Abstract: A control unit for an air conditioning system for a motor vehicle calculates a target blowing air temperature based on a temperature of a passenger's clothing detected by a no contact temperature sensor. An air conditioning operation is performed based on the calculated target blowing air temperature. In particular, when calculating the target temperature in the summer or in the winter season, a change of the detected temperature of the passenger's clothing is used, so that the change of detected temperature is reflected in the target temperature with a time delay.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: August 25, 2009
    Assignee: Denso Corporation
    Inventors: Yoshinori Ichishi, Tatsumi Kumada, Kouichi Itoh, Makoto Umebayashi, Yoshinori Yanagimachi, Kazushige Ogawa
  • Publication number: 20090170178
    Abstract: It is an object of the present invention to provide an electrical stimulating device for efficiently providing direct electrical stimulation to a large number of nerve cells in vitro without causing any injuries to such cells. The present invention provides a cell stimulating device which comprises: a first electrode serving as a positive or negative electrode that extends from one side of a culture vessel that is used for accommodating cultured cells to a point at which the first electrode is not in contact with the cultured cells or is in contact with the surfaces of the cultured cells; and a second electrode serving as a negative or positive electrode that extends from the other side of the culture vessel to a point at which the second electrode is not in contact with the cultured cells or is in contact with the surfaces of the cultured cells, wherein an electric field for stimulating cells is formed via the first electrode and the second electrode.
    Type: Application
    Filed: April 22, 2004
    Publication date: July 2, 2009
    Applicant: RIKEN
    Inventors: Miwako Ozaki, Kouichi Itoh
  • Patent number: 7536011
    Abstract: An encryption device performs elliptic curve encryption using a secret key. The encryption device includes an operation unit for performing scalar multiplication of a point on an elliptic curve a storage unit having a plurality of data storing areas and a determiner unit for determining, in accordance with a bit sequence of a given value (d) and with a random value (RNG), an address of one of the plurality of data storage areas that is to be coupled to the operation means for each scalar multiplication.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: May 19, 2009
    Assignee: Fujitsu Limited
    Inventors: Masahiko Takenaka, Tetsuya Izu, Kouichi Itoh, Naoya Torii
  • Publication number: 20090003598
    Abstract: The first route selection device re-arrays a plurality of extended key mask values at random according to the value of a random number generated by a random number generation device. An extended key operation device generates an exclusive logical OR of a plurality of the re-arrayed extended key mask values, a data string representing extended key and an input data string. The second route selection device re-arrays the data string of the exclusive logical OR by performing a re-array conversely with the first route selection device according to the value of the random number. A non-linear conversion device applies non-linear conversion to the re-arrayed data string and outputs a data string masked by a plurality of non-linear conversion mask values. The third route selection device re-arrays the masked data string by performing the same re-array as the first route selection device according to the value of the random number.
    Type: Application
    Filed: November 16, 2007
    Publication date: January 1, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Kouichi Itoh, Souichi Okada, Masahiko Takenaka
  • Publication number: 20080181395
    Abstract: In a cryptographic operation apparatus, the result of an encryption process, or decryption process, is obtained by disposing two operational circuits in parallel, each comprising four multiplying devices and an exclusive-OR device, and by processing an input data string in two cycles; or by processing an input data string by a single operational circuit in four cycles.
    Type: Application
    Filed: November 30, 2007
    Publication date: July 31, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Souichi OKADA, Kouichi ITOH
  • Publication number: 20080097217
    Abstract: A non-invasive (having sufficiently small diameter so as not to give much pain to a subject) ultrasonic ultrasound probe of high spatial resolution and high signal-to-noise ratio, an ultrasonograph using the probe, and an ultrasonography are provided. The ultrasound probe is inserted into the tissue under examination and transmits an ultrasonic wave.
    Type: Application
    Filed: September 12, 2005
    Publication date: April 24, 2008
    Applicant: MICROSONIC CO., LTD.
    Inventors: Kouichi Itoh, Tadashi Moriya, Takasuke Irie
  • Publication number: 20080025500
    Abstract: A randomly selected point on an elliptic curve is set as the initial value of a variable and calculation including a random point value is performed in an algorithm for calculating arbitrary scalar multiple operation on an elliptic curve when scalar multiplication and addition on an elliptic curve are defined, then a calculation value obtained as a result of including a random point is subtracted from the calculation result, whereby an intended scalar multiple operation value on an elliptic curve is determined.
    Type: Application
    Filed: July 24, 2007
    Publication date: January 31, 2008
    Inventors: Tetsuya Izu, Kouichi Itoh, Masahiko Takenaka