Abstract: A clock recovery circuit includes a delay line circuit configured to output a plurality of first clocks having different phases obtained by delaying an input data signal, a register circuit configured to determine and write received data in the input data signal based on the first clocks, and a control circuit configured to control the writing of the data in the register circuit based on transitions of the input data signal.

Abstract: A sensor device includes: a first portion that is formed of an inorganic semiconductor material, includes a control module, and is reusable; a second portion that is formed of an organic material and separably coupled to the first portion; and a sensor that is disposed in at least one of the first and second portions.

Abstract: A clock regeneration circuit includes a pattern detection circuit that detects a pattern having a time interval determined in advance in an input signal, and a signal processing circuit that generates a clock by variably controlling a time interval for oscillation based on the time interval of the detected pattern.

Abstract: A flip-flop circuit includes a data capture circuit that captures data based on a clock, a data hold circuit that holds an output of the data capture circuit based on the clock, and a timing control circuit that controls coupling between the output of the data capture circuit and the data hold circuit based on the clock, when the data capture circuit captures new data based on the clock, the timing control circuit performing control so as to temporarily interrupt the coupling between the output of the data capture circuit and the data hold circuit.

Abstract: A clock recovery circuit includes: a multi-phase clock generating circuit configured to generate multi-phase clocks having different phases; a plurality of switch elements configured to control coupling between each of the multi-phase clocks and an output node; and a switch control circuit configured to compare phases of the multi-phase clocks and input data and control, to an on-state, at least two switch elements of the plurality of switch elements corresponding to at least two clocks whose phase difference falls within a given range, wherein the at least two clocks selected through the at least two switch elements controlled to the on-state are subjected to phase interpolation to recover an output clock.

Abstract: A power amplifier circuit includes unit amplifiers (unit PAs) whose output terminals are connected to one another, among which a number of unit PAs to be operated is controlled by an amplitude signal indicative of an amplitude of an input signal, and which output output signals based on a phase signal indicative of a phase of the input signal and an output current controller which controls an output current of each of the unit PAs. Each unit PA includes a first transistor and a second transistor connected in series between the output terminal and a ground. The first transistor receives the phase signal at a gate. The second transistor receives at a gate a control signal generated by the output current controller and determines the output current flowing to the output terminal on the basis of the control signal.

Abstract: A clock recovery circuit includes a delay line circuit configured to output a plurality of first clocks having different phases obtained by delaying an input data signal, a register circuit configured to determine and write received data in the input data signal based on the first clocks, and a control circuit configured to control the writing of the data in the register circuit based on transitions of the input data signal.

Abstract: A clock recovery circuit includes: a multi-phase clock generating circuit configured to generate multi-phase clocks having different phases; a plurality of switch elements configured to control coupling between each of the multi-phase clocks and an output node; and a switch control circuit configured to compare phases of the multi-phase clocks and input data and control, to an on-state, at least two switch elements of the plurality of switch elements corresponding to at least two clocks whose phase difference falls within a given range, wherein the at least two clocks selected through the at least two switch elements controlled to the on-state are subjected to phase interpolation to recover an output clock.

Abstract: A sensor device includes: a first portion that is formed of an inorganic semiconductor material, includes a control module, and is reusable; a second portion that is formed of an organic material and separably coupled to the first portion; and a sensor that is disposed in at least one of the first and second portions.

Abstract: A flip-flop circuit includes a data capture circuit that captures data based on a clock, a data hold circuit that holds an output of the data capture circuit based on the clock, and a timing control circuit that controls coupling between the output of the data capture circuit and the data hold circuit based on the clock, when the data capture circuit captures new data based on the clock, the timing control circuit performing control so as to temporarily interrupt the coupling between the output of the data capture circuit and the data hold circuit.

Abstract: A clock regeneration circuit includes a pattern detection circuit that detects a pattern having a time interval determined in advance in an input signal, and a signal processing circuit that generates a clock by variably controlling a time interval for oscillation based on the time interval of the detected pattern.

Abstract: The present invention addresses the problem of providing a ship that can recognize the correct position of itself on the sea. A ship (100) comprises a recognition controller (160) that recognizes the position of the ship on the sea, the recognition controller (160) recognizing the position of the ship on the sea on the basis of relative distances between the ship (100) and a plurality of land-based targets. The recognition controller (160) captures an image (P1) of a structure (S1) and an image (P2) of a structure (S2) by using a first camera (161) and a second camera (162), respectively, and maneuvers the ship such that the sizes of the captured image (P1) and image (P2) do not change and thereby maintains a fixed point on the sea.

Abstract: A semiconductor integrated circuit includes a first transmission power mode configured to transmit by a first power, and a second transmission power mode configured to transmit by a second power smaller than the first power, the semiconductor integrated circuit. The semiconductor integrated circuit includes a first transistor configured to receive and amplify a transmission signal in the second transmission power mode, and an attenuator including a resistor element and a switching element, provided between an output of the first transistor and an output terminal, configured to control attenuation of an output signal of the first transistor.

Abstract: A power amplifier circuit includes unit amplifiers (unit PAs) whose output terminals are connected to one another, among which a number of unit PAs to be operated is controlled by an amplitude signal indicative of an amplitude of an input signal, and which output output signals based on a phase signal indicative of a phase of the input signal and an output current controller which controls an output current of each of the unit PAs. Each unit PA includes a first transistor and a second transistor connected in series between the output terminal and a ground. The first transistor receives the phase signal at a gate. The second transistor receives at a gate a control signal generated by the output current controller and determines the output current flowing to the output terminal on the basis of the control signal.

Abstract: A circuit includes a power wire, a switch element coupled to the power wire, an internal circuit coupled to the power wire via the switch element, a signal generation circuit coupled to the power wire and configured to generate a control signal based on a first reset signal outputted for a first period after power supply from a power source to the power wire starts, and a gate element configured to control the switch element based on the control signal and a second reset signal outputted for a second period longer than the first period after the power supply to the power wire starts.

Abstract: A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate. A heat dissipation structure is provided in the multi-layer wiring structure. The upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and the lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element.

Abstract: A transmitter includes a phase control circuit configured to receive a first and a second modulation signals, and a power amplifier configured to receive a third modulation signal. The phase control circuit includes a variable frequency divider, a frequency division ratio being controlled by the first modulation signal; a frequency modulation D/A converter configured to modulate the frequency by the second modulation signal; and a voltage controlled oscillator, including a varactor, configured to receive a first control voltage based on the first modulation signal and a second control voltage based on the second modulation signal. At least one of a capacitance value of the varactor of the voltage controlled oscillator, a control bit number of the frequency modulation D/A converter, and a bias current value of the frequency modulation D/A converter is changed based on a data transfer rate.

Abstract: A semiconductor integrated circuit includes a first transmission power mode configured to transmit by a first power, and a second transmission power mode configured to transmit by a second power smaller than the first power, the semiconductor integrated circuit. The semiconductor integrated circuit includes a first transistor configured to receive and amplify a transmission signal in the second transmission power mode, and an attenuator including a resistor element and a switching element, provided between an output of the first transistor and an output terminal, configured to control attenuation of an output signal of the first transistor.

Abstract: A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate. A heat dissipation structure is provided in the multi-layer wiring structure. The upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and the lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element.

Abstract: An amplifier is realized by a distributed-constant-type amplifier including an input-side transmission line and an output-side transmission line, and a plurality of unit circuits coupled between the input-side transmission line and the output-side transmission line, in which each of the plurality of unit circuits is formed by including an amplification circuit having a gain equal to or greater than one.