Abstract: In a PLL circuit, a threshold discriminator generates a control signal indicating a relative level of a control voltage. A controller outputs a controlling value based on the control signal. If the control signal indicates a high level when the controlling value specifies a control voltage-to-oscillation frequency correspondence relation whose upper and lower limits of oscillation frequency are highest, and if the control signal indicates a low level when the controlling value specifies a correspondence relation whose upper and lower limits of oscillation frequency are lowest, the controller outputs a predetermined controlling value. An oscillator has the correspondence relations set therein such that the correspondence relations have respective different upper and lower limits of oscillation frequency and are correlated with the respective controlling values.

Abstract: A common-mode voltage controller for adjusting common-mode voltages between a first buffer and a second buffer at a subsequent stage or a preceding stage of the first buffer in a signal transmission circuit, comprising: a first reference voltage generation unit for generating a common-mode voltage corresponding to the first buffer; a second reference voltage generation unit for generating a common-mode voltage corresponding to the second buffer at the subsequent stage or the preceding stage; and a control signal generation unit for generating a control signal for controlling a common-mode voltage of the first buffer according to a difference voltage between an output of the first reference voltage generation unit and an output of the second reference voltage generation unit, and giving the control signal to the first buffer and first reference voltage generation unit.

Abstract: A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each of the frequency dividing circuits includes a mixer, an adding circuit, and a phase circuit. The first frequency dividing circuit and the second frequency dividing circuit are coupled in loop shape via a first coupling circuit and a second coupling circuit. The first coupling circuit receives a first output signal of the first frequency dividing circuit to output a second external input signal to the second frequency dividing circuit, and the second coupling circuit receives a second output signal of the second frequency dividing circuit to output a first external input signal to the first frequency dividing circuit, and a clock frequency dividing circuit with a high loop gain and a wide lock range can be realized.

Abstract: LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.

Abstract: In a PLL circuit, a threshold discriminator generates a control signal indicating a relative level of a control voltage. A controller outputs a controlling value based on the control signal. If the control signal indicates a high level when the controlling value specifies a control voltage-to-oscillation frequency correspondence relation whose upper and lower limits of oscillation frequency are highest, and if the control signal indicates a low level when the controlling value specifies a correspondence relation whose upper and lower limits of oscillation frequency are lowest, the controller outputs a predetermined controlling value. An oscillator has the correspondence relations set therein such that the correspondence relations have respective different upper and lower limits of oscillation frequency and are correlated with the respective controlling values.

Abstract: An amplifier is realized by a distributed-constant-type amplifier including an input-side transmission line and an output-side transmission line, and a plurality of unit circuits coupled between the input-side transmission line and the output-side transmission line, in which each of the plurality of unit circuits is formed by including an amplification circuit having a gain equal to or greater than one.

Abstract: There are provided a peaking detection part detecting a peaking amount in an output part of an inductor peaking circuit and a control signal generation part varying a circuit parameter of the inductor peaking circuit based on the peaking amount detected by the peaking detection part. Particularly, the inductor peaking circuit has inductors and resistors inserted in series between the output part and a power supply, and capacitances coupled in parallel between the output part and an earth (GND), and depending on respective values of these inductors, resistors and capacitances, it is possible to suppress a peaking generated in the output part.

Abstract: In order to provide a timing adjustment circuit capable of transmitting/receiving data without being affected by process unevenness and power voltage/temperature fluctuations even at a high data transfer rate, the phase of data outputted by a data transmitting unit is compared with the phase of a clock for regulating a data receiving timing of a data receiving unit, and the phase of a clock for regulating a data transmitting timing of the data transmitting unit is adjusted according to the comparison result.

Abstract: A flip-flop circuit that captures an input signal in sync with a clock, has a first gate outputting a first signal corresponding with input signal; a second gate generating a second signal of a first predetermined level in response to a first level of clock and causing the second signal to be a level of first signal in response to a second level of clock; and a third gate outputting a third signal of second signal in response to the second level of clock. Further the flip-flop circuit has a first inversion feedback circuit between the third and second signal terminals, that is activated in response to the second level of clock and latches the third signal together with third gate; and level fixing circuit that fixes the first signal terminal at a second predetermined level with a time delay after the clock changes to the second level.

Abstract: There are provided a peaking detection part detecting a peaking amount in an output part of an inductor peaking circuit and a control signal generation part varying a circuit parameter of the inductor peaking circuit based on the peaking amount detected by the peaking detection part. Particularly, the inductor peaking circuit has inductors and resistors inserted in series between the output part and a power supply, and capacitances coupled in parallel between the output part and an earth (GND), and depending on respective values of these inductors, resistors and capacitances, it is possible to suppress a peaking generated in the output part.

Abstract: A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each of the frequency dividing circuits includes a mixer, an adding circuit, and a phase circuit. The first frequency dividing circuit and the second frequency dividing circuit are coupled in loop shape via a first coupling circuit and a second coupling circuit. The first coupling circuit receives a first output signal of the first frequency dividing circuit to output a second external input signal to the second frequency dividing circuit, and the second coupling circuit receives a second output signal of the second frequency dividing circuit to output a first external input signal to the first frequency dividing circuit, and a clock frequency dividing circuit with a high loop gain and a wide lock range can be realized.

Abstract: A common-mode voltage controller for adjusting common-mode voltages between a first buffer and a second buffer at a subsequent stage or a preceding stage of the first buffer in a signal transmission circuit, comprising: a first reference voltage generation unit for generating a common-mode voltage corresponding to the first buffer; a second reference voltage generation unit for generating a common-mode voltage corresponding to the second buffer at the subsequent stage or the preceding stage; and a control signal generation unit for generating a control signal for controlling a common-mode voltage of the first buffer according to a difference voltage between an output of the first reference voltage generation unit and an output of the second reference voltage generation unit, and giving the control signal to the first buffer and first reference voltage generation unit.

Abstract: A clock distribution circuit for suitably generating, transmitting, and receiving clock signals used in circuits that are configured with the same circuit topology is provided. The clock distribution circuit has a transmission buffer circuit that transmits a clock signal and an amplitude amplification buffer circuit that amplifies the amplitude of cross-coupling connections inserted in parallel with the transmission buffer circuit on a transmission path for the clock signal. Wherein the number of transistors having the same conductivity type as the transistors of a differing conductivity type of the transmission buffer circuit and that of the transistors of a differing conductivity type of the amplitude amplification buffer circuit are the same. At least one transistor is provided as a bias adjustment transistor for adjusting bias in each of the transmission buffer circuit and the amplitude amplification buffer circuit, respectively, and bias adjustments are made simultaneously.

Abstract: When an LSI is connected to a plurality of memories that perform data transfers by a handshake access method, the need for the LSI to continuously output an access signal to a memory for a long period of time is eliminated. A hold circuit is provided between the LSI and the memory. The LSI outputs an access signal for specifying address information and a memory via a bus for a predetermined time period. The hold circuit holds the access signal and continually outputs the held access signal to the memory via a signal line connecting the hold circuit and the memory, in place of the LSI. After waiting until preparation for data transfer has been completed in the storage apparatus, the LSI again outputs an access signal and performs reading or writing of data.

Abstract: A clock distribution circuit for suitably generating, transmitting, and receiving clock signals used in circuits that are configured with the same circuit topology is provided. The clock distribution circuit has a transmission buffer circuit that transmits a clock signal and an amplitude amplification buffer circuit that amplifies the amplitude of cross-coupling connections inserted in parallel with the transmission buffer circuit on a transmission path for the clock signal. Wherein the number of transistors having the same conductivity type as the transistors of a differing conductivity type of the transmission buffer circuit and that of the transistors of a differing conductivity type of the amplitude amplification buffer circuit are the same. At least one transistor is provided as a bias adjustment transistor for adjusting bias in each of the transmission buffer circuit and the amplitude amplification buffer circuit, respectively, and bias adjustments are made simultaneously.

Abstract: In order to provide a timing adjustment circuit capable of transmitting/receiving data without being affected by process unevenness and power voltage/temperature fluctuations even at a high data transfer rate, the phase of data outputted by a data transmitting unit is compared with the phase of a clock for regulating a data receiving timing of a data receiving unit, and the phase of a clock for regulating a data transmitting timing of the data transmitting unit is adjusted according to the comparison result.

Abstract: LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.

Abstract: A flip-flop circuit that captures an input signal in sync with a clock, has a first gate outputting a first signal corresponding with input signal; a second gate generating a second signal of a first predetermined level in response to a first level of clock and causing the second signal to be a level of first signal in response to a second level of clock; and a third gate outputting a third signal of second signal in response to the second level of clock. Further the flip-flop circuit has a first inversion feedback circuit between the third and second signal terminals, that is activated in response to the second level of clock and latches the third signal together with third gate; and level fixing curcuit that fixes the first signal terminal at a second predetermined level with a time delay after the clock changes to the second level.

Abstract: A sputtering target is provided that includes SiC and metallic Si and has an atomic ratio of C to Si of from 0.5 to 0.95 and a density of from 2.75×103 kg/m3 to 3.1×103 kg/m3. The sputtering target is capable of forming at high speed a film that contains SiO2 as the main component and has a low refractive index. The sputtering target can be produced by a process in which a molded product of SiC is impregnated with molten Si.

Abstract: A cylindrical target having a cylindrical backing tube and hollow cylindrical target material disposed on an outer circumference of the cylindrical backing tube. The backing tube and the target material are joined via an electroconductive felt present beteween the backing tube and the target material.