Abstract: A master slice semiconductor IC has a SOI substrate and a plurality of basic cells arranged in a matrix on the SOI substrate. The basic cell includes a two-input NAND gate and a diode forward biased between one of power supply lines and the NAND gate. The diode has a P-N junction extending between the top surface of a semiconductor layer and the insulator layer underlying the semiconductor layer. The diode reduces the supply voltage by the forward drop voltage thereof to reduce power consumption in the NAND gate, and the SOI structure of the basic cell prevents reduction of integration density and operational speed.

Abstract: In a CMOS SRAM cell formed on an SOI substrate and including a flip-flop having first and second NMOS and PMOS transistors, transfer gates having first and seconf MOS transistors, and a word line section, characterized in that:the word line section extends along a predetermined direction; that source and drain diffusion layer regions of the first and second NMOS and PMOS transistors are arranged along the predetermined direction, and gates of these NMOS and PMOS transistors are arranged on channel regions thereof in a direction perpendicular to the predetermined direction; that the gates of the first and second NMOS transistors are electrically connected to the gates of the first and second PMOS transistors, respectively; and that in regions between the gates of the first and second NMOS transistors on the channel regions and the gates of the first and second PMOS transistors on the channel regions, each of the drain diffusion layer regions of the fisrt and second NMOS and PMOS transistors, and each one of th

Abstract: In a semiconductor integrated circuit having an internal wiring conductor for transferring an internal signal, an intermediate voltage generator generates an intermediate voltage equal to a half of a power supply voltage, and a driver circuit receives the intermediate voltage and the internal signal, for generating to the internal wiring conductor a positive/negative pulse signal having the intermediate voltage as a reference level, in response to a rising/falling edge of the internal signal. A receiver circuit receives the positive/negative pulse signal transferred through the internal wiring conductor. An output of the receiver circuit is set in response to a positive pulse of the positive/negative pulse signal, and reset in response to a negative pulse of the positive/negative pulse signal.

Abstract: The invention provides a semiconductor integrated circuit including a substrate, and a plurality of block cells arranged on the substrate and including a plurality of basic cells. Each of the basic cells includes a plurality of CMOS transistors. At least one of the CMOS transistors is an asymmetrical one in which one of a source diffusion layer or a drain diffusion layer has a lightly doped drain (LDD) structure or a deep doped drain (DDD) structure.

Abstract: In a semiconductor device where a CMOS circuit and a bipolar circuit are mixed, the bipolar circuit is operated between a first power supply voltage and a second power supply voltage, and the CMOS circuit and a level conversion circuit between a CMOS level and a bipolar level are operated between the first power supply voltage and a third power supply voltage. The third power supply voltage is between the first and second power supply voltages.

Abstract: A semiconductor device has protective devices formed in a P-type semiconductive region maintained at a ground potential and disposed adjacent to bonding pads connected to internal circuitry through respective signal lines. A plurality of first N+ diffusion regions connected to respective signal lines and a second diffusion region connected to a ground line are disposed in the P-type semiconductive region. A separating region having a thick insulating layer is disposed between the first diffusion regions and the second diffusion region. The protective devices formed as NPN transistors have a common emitter at the second N+ diffusion region, which has enough area for storing and discharging electric charges to the ground, while the occupied area of the protective devices is maintained small. The protective devices can be formed as so-called field MOS transistors having a common source.

Abstract: In an unused unit cell of a gate array integrated semiconductor device, a P-type semiconductor region is connected to a ground potential connection and an N-type semiconductor region is connected to a positive power supply connection, thereby reversely-biasing the P-type and N-type semiconductor regions.

Abstract: Herein disclosed is a bipolar-CMOS semiconductor circuit having a semiconductor substrate, an N.sup.- epitaxial layer formed on the semiconductor substrate, an N well formed in the N.sup.- epitaxial layer, a P well formed in the N.sup.- epitaxial layer, a power supply terminal to which the positive potential is to be supplied, a ground potential terminal, an input terminal, an output terminal, an NPN bipolar transistor formed in the N.sup.- epitaxial layer, the NPN bipolar transistor having the N.sup.- epitaxial layer as the collector thereof and having an emitter connected to the output terminal, a P-channel type MOS transistor formed in the N well and being connected between the power supply terminal and the base of the NPN bipolar transistor, the gate of the P-channel type MOS transistor being connected to the input terminal, and both the N well for the P-channel type MOS transistor and the N.sup.