Patents by Inventor Kouichi Saitou
Kouichi Saitou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210234038Abstract: A semiconductor device includes: a silicon carbide semiconductor layer of a first conductivity type disposed on a semiconductor substrate; a first impurity region of a second conductivity type located on a surface of the semiconductor layer, the first impurity region surrounding the active region; a plurality of rings of the second conductivity type surrounding the first impurity region; a first insulating film disposed to cover a portion of the first impurity region and the plurality of rings, the first insulating film having a first aperture; a first electrode within the first aperture, the first electrode; a second insulating film disposed to surround the active region, the second insulating film having a higher moisture resistance than the first insulating film; a third insulating film covering a portion of the first electrode and the second insulating film, and a second electrode disposed on the rear face of the semiconductor substrate.Type: ApplicationFiled: January 22, 2021Publication date: July 29, 2021Inventors: Masao UCHIDA, Kouichi SAITOU, Takashi HASEGAWA, Takayuki WAKAYAMA
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Patent number: 11024706Abstract: A semiconductor device includes a silicon carbide semiconductor layer, a termination region disposed in the silicon carbide semiconductor layer, an insulating film covering part of the termination region, an electrode disposed on the silicon carbide semiconductor layer, a seal ring disposed on remaining part of the termination region and surrounding the electrode, and a passivation film covering the insulating film and the seal ring. Assuming that an outer peripheral end of the seal ring and an outer peripheral end of the passivation film have distance L2 at a side of the silicon carbide semiconductor layer, the outer peripheral end of the seal ring and the outer peripheral end of the passivation film have distance L1 at a corner, and the outer peripheral end of the passivation film at the corner has radius of curvature R1, L1>L2 and R1?L2 are satisfied.Type: GrantFiled: December 26, 2019Date of Patent: June 1, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Masao Uchida, Kouichi Saitou, Takashi Hasegawa
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Patent number: 10978367Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.Type: GrantFiled: August 24, 2018Date of Patent: April 13, 2021Assignee: PANASONIC INTELLECTUAL PROPRETY MANAGEMENT CO., LTD.Inventors: Chiaki Kudou, Takashi Hasegawa, Kouichi Saitou
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Patent number: 10763331Abstract: A semiconductor device includes a bulk substrate, and an epitaxial layer formed on a surface of the bulk substrate. A part of the surface of the bulk substrate is an alignment region including an alignment pattern defined by at least one recess or one protrusion. An ion-injected layer is formed in at least a part of the alignment region.Type: GrantFiled: September 25, 2018Date of Patent: September 1, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Kouichi Saitou
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Publication number: 20200266268Abstract: A semiconductor device includes a silicon carbide semiconductor layer, a termination region disposed in the silicon carbide semiconductor layer, an insulating film covering part of the termination region, an electrode disposed on the silicon carbide semiconductor layer, a seal ring disposed on remaining part of the termination region and surrounding the electrode, and a passivation film covering the insulating film and the seal ring. Assuming that an outer peripheral end of the seal ring and an outer peripheral end of the passivation film have distance L2 at a side of the silicon carbide semiconductor layer, the outer peripheral end of the seal ring and the outer peripheral end of the passivation film have distance L1 at a corner, and the outer peripheral end of the passivation film at the corner has radius of curvature R1, L1>L2 and R1?L2 are satisfied.Type: ApplicationFiled: December 26, 2019Publication date: August 20, 2020Inventors: MASAO UCHIDA, KOUICHI SAITOU, TAKASHI HASEGAWA
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Patent number: 10439034Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source line. The gate electrode is disposed on the gate insulating layer. The interlayer insulating layer covers the gate electrode. The contact hole penetrates the gate insulating layer and the interlayer insulating layer, causes a portion of the surface of the semiconductor substrate to be exposed, and includes an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer. The metal layer covers an upper surface of the interlayer insulating layer, the inner surface of the contact hole, and at least part of the portion of the surface of the semiconductor substrate exposed by the contact hole.Type: GrantFiled: November 13, 2018Date of Patent: October 8, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takashi Hasegawa, Kouichi Saitou, Chiaki Kudou
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Publication number: 20190165119Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source line. The gate electrode is disposed on the gate insulating layer. The interlayer insulating layer covers the gate electrode. The contact hole penetrates the gate insulating layer and the interlayer insulating layer, causes a portion of the surface of the semiconductor substrate to be exposed, and includes an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer. The metal layer covers an upper surface of the interlayer insulating layer, the inner surface of the contact hole, and at least part of the portion of the surface of the semiconductor substrate exposed by the contact hole.Type: ApplicationFiled: November 13, 2018Publication date: May 30, 2019Inventors: TAKASHI HASEGAWA, KOUICHI SAITOU, CHIAKI KUDOU
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Publication number: 20190103463Abstract: A semiconductor device includes a bulk substrate, and an epitaxial layer formed on a surface of the bulk substrate. A part of the surface of the bulk substrate is an alignment region including an alignment pattern defined by at least one recess or one protrusion. An ion-injected layer is formed in at least a part of the alignment region.Type: ApplicationFiled: September 25, 2018Publication date: April 4, 2019Inventor: KOUICHI SAITOU
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Publication number: 20190080976Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.Type: ApplicationFiled: August 24, 2018Publication date: March 14, 2019Inventors: CHIAKI KUDOU, TAKASHI HASEGAWA, KOUICHI SAITOU
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Patent number: 10043299Abstract: In an image processing apparatus, a spatial and temporal clipping standards, and a spatial and temporal combining standards are prepared. The image processing apparatus is provided with a CPU that is configured to clip plural moving images from one moving image in accordance with a spatial and/or temporal clipping standard, and combine spatially or temporally the clipped moving images with each other in accordance with a spatial and/or temporal combining standard, thereby generating a new moving image.Type: GrantFiled: October 8, 2015Date of Patent: August 7, 2018Assignee: CASIO COMPUTER CO., LTD.Inventor: Kouichi Saitou
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Publication number: 20180215895Abstract: Provided is a rubber composition that can reduce unvulcanized viscosity and has excellent wear resistance and low-loss property. To this end, a rubber composition contains silica, in which the silica has a pH of 10.0 or less before washing and a pH of 4.0 or more after washing, and contains Al2O3, and the content in mass % of Al2O3, a BET specific surface area in m2/g of the silica and a CTAB specific surface area in m2/g of the silica satisfy: Al2O3?10.9×(BET specific surface area/CTAB specific surface area)>?11.0.Type: ApplicationFiled: June 10, 2016Publication date: August 2, 2018Applicant: BRIDGESTONE CORPORATIONInventor: Kouichi SAITOU
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Patent number: 10017625Abstract: The present invention provides a rubber composition that can offer excellent abrasion resistance when applied to a tire member such as a tread, without deteriorating rolling resistance. To solve the problem, a rubber composition according to the present invention contains a rubber component, hydrous silicate, and a surfactant, in which the hydrous silicate is modified by the surfactant before being kneaded with the rubber component.Type: GrantFiled: May 8, 2013Date of Patent: July 10, 2018Assignee: BRIDGESTONE CORPORATIONInventor: Kouichi Saitou
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Publication number: 20180151719Abstract: A silicon carbide semiconductor device includes a first conductivity type silicon carbide substrate having an active region and a termination region surrounding the active region, a plurality of unit cells located in the active region, and a termination structure located in the termination region. Each unit cell is provided with a transistor structure. The termination structure includes the silicon carbide semiconductor layer, a second conductivity type second body region surrounding the active region, one or more second conductivity type rings surrounding the second body region, one or more outer-circumferential upper source electrodes surrounding the active region, and an upper gate electrode. The silicon carbide semiconductor device further includes a first protective film and a second protective film.Type: ApplicationFiled: November 14, 2017Publication date: May 31, 2018Inventors: TSUNEICHIRO SANO, ATSUSHI OHOKA, TSUTOMU KIYOSAWA, OSAMU ISHIYAMA, TAKAYUKI WAKAYAMA, KOUICHI SAITOU, TAKASHI HASEGAWA, DAISUKE SHINDO, OSAMU KUSUMOTO
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Patent number: 9985125Abstract: A silicon carbide semiconductor device includes a first conductivity type silicon carbide substrate having an active region and a termination region surrounding the active region, a plurality of unit cells located in the active region, and a termination structure located in the termination region. Each unit cell is provided with a transistor structure. The termination structure includes the silicon carbide semiconductor layer, a second conductivity type second body region surrounding the active region, one or more second conductivity type rings surrounding the second body region, one or more outer-circumferential upper source electrodes surrounding the active region, and an upper gate electrode. The silicon carbide semiconductor device further includes a first protective film and a second protective film.Type: GrantFiled: November 14, 2017Date of Patent: May 29, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Tsuneichiro Sano, Atsushi Ohoka, Tsutomu Kiyosawa, Osamu Ishiyama, Takayuki Wakayama, Kouichi Saitou, Takashi Hasegawa, Daisuke Shindo, Osamu Kusumoto
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Patent number: 9773924Abstract: A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate.Type: GrantFiled: April 2, 2016Date of Patent: September 26, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Masao Uchida, Kouichi Saitou, Takayuki Wakayama
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Patent number: 9723221Abstract: An imaging device shoots a common subject in synchronization with other imaging devices. The imaging device includes a processor. The processor receives states of the other imaging devices, compare an own state of the imaging device with the received states of the other imaging devices, and determine whether the imaging device functions as a main device or a subordinate device for setting an imaging condition. When the processor determines that the imaging device functions as the main device, the processor sends imaging information acquired or determined by the imaging device for shooting the common subject to the subordinate devices. When the processor determines that the imaging device functions as the subordinate device, the processor sets the imaging condition in the imaging device based on the imaging information received from the main device.Type: GrantFiled: August 5, 2015Date of Patent: August 1, 2017Assignee: CASIO COMPUTER CO., LTD.Inventors: Jun Iijima, Kazuya Nara, Kouichi Saitou, Toshiya Kiso, Takuya Yamada
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Publication number: 20160315203Abstract: A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate.Type: ApplicationFiled: April 2, 2016Publication date: October 27, 2016Inventors: MASAO UCHIDA, KOUICHI SAITOU, TAKAYUKI WAKAYAMA
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Publication number: 20160308072Abstract: A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface of the semiconductor substrate, a guard ring region having a second conductivity type and disposed within the silicon carbide semiconductor layer, a floating region having the second conductivity type and disposed within the silicon carbide semiconductor layer, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface of the semiconductor substrate, wherein the guard ring region and the floating region each include a pair of a high-concentration region having the second conductivity type and a low-concentration region having the second conductivity type.Type: ApplicationFiled: April 1, 2016Publication date: October 20, 2016Inventors: MASAO UCHIDA, KOUICHI SAITOU, TAKAYUKI WAKAYAMA, MASASHI HAYASHI, TATSUYA KUNISATO
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Publication number: 20160189412Abstract: In an image processing apparatus, a spatial and temporal clipping standards, and a spatial and temporal combining standards are prepared. The image processing apparatus is provided with a CPU that is configured to clip plural moving images from one moving image in accordance with a spatial and/or temporal clipping standard, and combine spatially or temporally the clipped moving images with each other in accordance with a spatial and/or temporal combining standard, thereby generating a new moving image.Type: ApplicationFiled: October 8, 2015Publication date: June 30, 2016Applicant: CASIO COMPUTER CO., LTD.Inventor: Kouichi SAITOU
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Patent number: 9313472Abstract: An image capture apparatus includes a second communication control unit, a first communication control unit and a communication unit. The second communication control unit controls the communication unit so as to transmit information of a face image serving as identification information to identify a specific subject to one other image capture apparatus. The first communication control unit controls the communication unit so as to receive from the other image capture apparatus, from among images captured by the image capture unit included in each image capture apparatus, an image in which a subject designated by the transmitted face image is captured.Type: GrantFiled: February 26, 2014Date of Patent: April 12, 2016Assignee: CASIO COMPUTER CO., LTD.Inventor: Kouichi Saitou