Abstract: The present invention relates to an organic EL device having at least an anodic electrode, a hole transport layer, a light emitting layer, an electron transport layer, a cathodic electrode, and a capping layer in this order, in which the capping layer contains an amine compound having a benzazole ring structure represented by the following general formula (A-1).

Abstract: It is an object of the present invention to provide a compound for a capping layer that has a high refractive index and a low extinction coefficient in a range of 450 nm to 750 nm to improve the light extraction efficiency of an organic EL element. The present invention has focused on the fact that compounds having a benzene skeleton at the center thereof are excellent in stability and also durability in the form of a thin film, and that the refractive index thereof can be improved by modifying the molecular structure, and thus, molecules have been designed. Provided is a compound represented by a general formula (1), and an organic EL element with excellent luminance efficiency is obtained by using that compound as a constituent material of a capping layer.

Abstract: To provide an organic EL device having low driving voltage, high luminous efficiency, and particularly a long lifetime by combining various materials for an organic EL device having excellent hole and electron injection/transport performances, electron blocking ability, stability in a thin-film state, and durability as materials for an organic EL device having high luminous efficiency and high durability so as to allow the respective materials to effectively reveal their characteristics. In the organic EL device having at least an anode, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and a cathode, in this order, the hole injection layer includes an arylamine compound of the following general formula (1) and a radialene derivative of the following general formula (2).

Abstract: A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.

Abstract: A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.

Abstract: A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.

Abstract: A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.

Abstract: A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.

Abstract: An electric compressor includes a compression part, an electric motor, an inverter device, and a housing. The inverter device includes an inverter circuit, a noise reduction unit, and a circuit board. The noise reduction unit includes a common mode choke coil and a smoothing capacitor. The common mode choke coil includes an annular core, a pair of winding wires, and an annular electrical conductor. The electrical conductor is split into a first metal plate and a second metal plate in a circumferential direction. The first metal plate is thermally coupled to the housing. The second metal plate is electrically connected to the first metal plate. An electrical resistance value of the first metal plate is larger than that of the second metal plate.

Abstract: A semiconductor device of a hybrid type includes: a light-emitting element forming a power loop; a semiconductor integrated circuit element including a switching element; and a bypass capacitor. The light-emitting element and the switching element constitute a layered body in which respective principal surfaces of the light-emitting element and the switching element are layered in parallel and face-to-face. The bypass capacitor includes one electrode connected to a lower element of the layered body, and an other electrode connected to an upper element of the layered body. In a plan view, when a direction from the one electrode to the other electrode inside the bypass capacitor is a first direction, the bypass capacitor is arranged so that a side of the bypass capacitor parallel to the first direction includes a portion that is parallel to and faces one peripheral side of the layered body.

Abstract: A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.

Abstract: A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: An electric compressor includes a compression part, an electric motor, an inverter device, and a housing. The inverter device includes an inverter circuit, a noise reduction unit, and a circuit board. The noise reduction unit includes a common mode choke coil and a smoothing capacitor. The common mode choke coil includes an annular core, a pair of winding wires, and an annular electrical conductor. The electrical conductor is split into a first metal plate and a second metal plate in a circumferential direction. The first metal plate is thermally coupled to the housing. The second metal plate is electrically connected to the first metal plate. An electrical resistance value of the first metal plate is larger than that of the second metal plate.

Abstract: A vehicle electric compressor includes a compression part, an electric motor, and an inverter device. The inverter device includes a noise reduction unit that includes a common mode choke coil. The common mode choke coil includes a core, a first winding wire, a second winding wire, and an electrical conductor that covers the core. The electrical conductor has a first insulation layer and a second insulation layer. The first insulation layer, the electrical conductor, and the second insulation layer form a laminated body including a loop-shaped portion that covers the core and a joint portion.

Abstract: A high-frequency amplifier includes: a carrier amplifier amplifying a first signal; a peak amplifier amplifying a second signal; a first transmission line connected between output terminals of the carrier amplifier and the peak amplifier, and having an electrical length equal to one-quarter wavelength of a center frequency in the predetermined frequency band; a second transmission line connected between one end of the first transmission line and the output terminal of the high-frequency amplifier, and having an electrical length equal to one-quarter wavelength of the center frequency; and an impedance compensation circuit with one end connected to a node between the first transmission line and the second transmission line. At the center frequency, an imaginary part of an impedance during viewing of the impedance compensation circuit from the node is opposite in polarity from an imaginary part of an impedance during viewing of the second transmission line from the node.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A high-frequency amplifier includes: a carrier amplifier amplifying a first signal; a peak amplifier amplifying a second signal; a first transmission line connected between output terminals of the carrier amplifier and the peak amplifier, and having an electrical length equal to one-quarter wavelength of a center frequency in the predetermined frequency band; a second transmission line connected between one end of the first transmission line and the output terminal of the high-frequency amplifier, and having an electrical length equal to one-quarter wavelength of the center frequency; and an impedance compensation circuit with one end connected to a node between the first transmission line and the second transmission line. At the center frequency, an imaginary part of an impedance during viewing of the impedance compensation circuit from the node is opposite in polarity from an imaginary part of an impedance during viewing of the second transmission line from the node.