Abstract: The present invention provides a permanent magnet rotating electric machine that comprises a stator, into which concentrated wound armature windings are inserted in such a way as to surround a plurality of teeth formed in a stator core, and a rotor having rare earth permanent magnets inserted into a plurality of permanent magnet holes, which are formed in a rotor core and used for accommodating permanent magnets. In this permanent magnet rotating electric machine, the permanent magnets are each shaped like a convex “V” or “U” with respect to the shaft of the rotor. Moreover, a ratio of the width W1 of an interpole core between the permanent magnets to the width Xg of the gap between the stator core and the rotor core is set in such a manner as to satisfy the following condition: 0.8≦W1/Xg≦13.2. Thus, even when this rotating electric machine is driven by a position sensorless inverter in the case of 120 degree energization, the system efficiency is enhanced.

Abstract: A semiconductor integrated circuit device includes a main memory portion, a sub memory portion including a plurality of memory cell groups and a bidirectional data transfer circuit provided between the main memory portion and the sub memory portion. A bi-directional data transfer between an arbitrary area of the main memory portion and the plurality of the memory cell groups, and a read or write operation are performed simultaneously. Therefore, the semiconductor integrated circuit device has a main memory suitable for being accessed from a plurality of memory masters or data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion composed of a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, the sub memory portion being constituted with a plurality of memory cell groups, and a plurality of registers provided such that different data input/output modes are set independently for the plurality of the memory cell groups. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: The present invention provides a semiconductor memory device having a dynamic random access memory and a static random access memory for transmissions of data between the dynamic random access memory and the static random access memory, wherein there are provided a plurality of dynamic random access memory arrays, each of which comprises a pair of a dynamic random access memory cell array and a sense amplifier for data read/write operation to the dynamic random access memory cell array, and there is provided at least a static random access memory array, and the plurality of dynamic random access memory arrays and the at least a static random access memory array are connected through at least a data transmission bus.

Abstract: A semiconductor integrated circuit device includes a main memory portion and a sub memory portion including a plurality of memory cell groups, wherein a bi-directional data transfer is performed between an arbitrary area of the main memory portion and each of the plurality of the memory cell groups and the plurality of the memory cell groups function as independent cache memories, respectively. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion constructed with memory cells arranged in a plurality of rows and in a plurality of columns, a sub memory portion constructed with a plurality of memory cells arranged in a plurality of rows and in a plurality of columns and a bi-directional data transfer circuit for connecting the main memory portion and the sub memory portion through data transfer bus lines, respectively, wherein the data transfer bus lines in a memory cell area of the main memory portion are arranged in parallel to bit lines in a column direction and connected to the bit lines through a column selection circuit. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.

Abstract: A semiconductor integrated circuit device is comprised a main memory portion, a sub memory portion composed of a plurality of memory cell groups and a bi-directional data transfer circuit provided between the main memory portion and the sub memory portion, wherein power source voltages of the main memory portion and the sub memory portion are different from each other. Therefore, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processors.