Patents by Inventor Kouros Ghandehari
Kouros Ghandehari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8309457Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).Type: GrantFiled: October 27, 2011Date of Patent: November 13, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
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Publication number: 20120045888Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).Type: ApplicationFiled: October 27, 2011Publication date: February 23, 2012Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
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Patent number: 8048797Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).Type: GrantFiled: May 19, 2009Date of Patent: November 1, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
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Patent number: 7977797Abstract: The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.Type: GrantFiled: August 11, 2009Date of Patent: July 12, 2011Assignee: Spansion LLCInventors: Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari
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Patent number: 7888269Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.Type: GrantFiled: October 24, 2005Date of Patent: February 15, 2011Assignees: Spansion LLC, GlobalFoundries, Inc.Inventors: Kouros Ghandehari, Hirokazu Tokuno, David Matsumoto, Christopher H. Raeder, Christopher Foster, Weidong Qian, Minh Van Ngo
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Publication number: 20100009536Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).Type: ApplicationFiled: May 19, 2009Publication date: January 14, 2010Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
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Publication number: 20090294969Abstract: The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.Type: ApplicationFiled: August 11, 2009Publication date: December 3, 2009Inventors: Wenmei LI, Angela T. HUI, Dawn HOPPER, Kouros GHANDEHARI
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Patent number: 7572727Abstract: The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.Type: GrantFiled: September 2, 2004Date of Patent: August 11, 2009Assignee: Spansion LLCInventors: Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari
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Patent number: 7538026Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).Type: GrantFiled: April 4, 2005Date of Patent: May 26, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
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Patent number: 7507661Abstract: A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.Type: GrantFiled: August 11, 2004Date of Patent: March 24, 2009Assignee: Spansion LLCInventors: Emmanuil H. Lingunis, Ning Cheng, Mark Ramsbey, Kouros Ghandehari, Anna Minvielle, Hung-Eil Kim
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Patent number: 7361587Abstract: The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop contact formation process in which a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.Type: GrantFiled: September 2, 2004Date of Patent: April 22, 2008Assignee: Spansion, LLCInventors: Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari
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Publication number: 20070093070Abstract: A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.Type: ApplicationFiled: October 24, 2005Publication date: April 26, 2007Inventors: Kouros Ghandehari, Hirokazu Tokuno, David Matsumoto, Christopher Raeder, Christopher Foster, Weidong Qian, Minh Ngo
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Patent number: 7070911Abstract: A structure and method for reducing standing waves in a photoresist during manufacturing of a semiconductor is presented. Embodiments of the present invention include a method for reducing standing wave formation in a photoresist during manufacturing a semiconductor device comprising depositing a first anti-reflective coating having an extinction coefficient above a material, and depositing a second anti-reflective coating having an extinction coefficient above the first anti-reflective coating, such that the first anti-reflective coating and the second anti-reflective coating reduce the formation of standing waves in a photoresist during a lithography process.Type: GrantFiled: January 23, 2003Date of Patent: July 4, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Dawn Hopper, Kouros Ghandehari, Minh Van Ngo
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Publication number: 20060035459Abstract: A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.Type: ApplicationFiled: August 11, 2004Publication date: February 16, 2006Inventors: Emmanuil Lingunis, Ning Cheng, Mark Ramsbey, Kouros Ghandehari, Anna Minvielle, Hung-Eil Kim
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Patent number: 6994939Abstract: A method and system of making a mask with a transparent substrate thereon is provided. A first resolution enhancement structure is formed on the first portion of the transparent substrate. A second resolution enhancement structure is formed on a second portion of the transparent substrate, with the second resolution enhancement structure different from the first resolution enhancement structure.Type: GrantFiled: October 29, 2002Date of Patent: February 7, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Kouros Ghandehari, Jean Y. Yang, Christopher A. Spence
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Patent number: 6962849Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.Type: GrantFiled: December 5, 2003Date of Patent: November 8, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Tazrien Kamal, Weidong Qian, Kouros Ghandehari, Taraneh Jamali-Beh, Mark T. Ramsbey, Ashok M. Khathuria
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Patent number: 6902851Abstract: A phase-shifting mask for a photolithographic process includes a transparent material having first and second trenches. The first trench has a first depth and the second trench has a second depth deeper than the first depth. The phase-shifting mask is suitable for testing the effect of lights of two wavelengths on a layer of photoresist.Type: GrantFiled: January 16, 2002Date of Patent: June 7, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Carl P. Babcock, Kouros Ghandehari
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Patent number: 6894342Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over at least one memory cell and over the substrate. The structure further comprises a first antireflective coating layer situated over the interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises a second antireflective coating layer situated directly over the first anti reflective coating layer. Either the first antireflective coating layer or second antireflective coating layer must be a silicon-rich layer. The first antireflective coating layer and the second antireflective coating may form a UV radiation blocking layer having a UV transparency less than approximately 1.0 percent, for example.Type: GrantFiled: June 12, 2003Date of Patent: May 17, 2005Assignee: Spansion LLCInventors: Angela Hui, Minh V. Ngo, Ning Cheng, Jaeyong Park, Jean Y. Yang, Hirokazu Tokuno, Kouros Ghandehari, Hidehiko Shiraiwa
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Patent number: 6872609Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. A Safier material is utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.Type: GrantFiled: January 12, 2004Date of Patent: March 29, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Tazrien Kamal, Weidong Qian, Kouros Ghandehari, Taraneh Jamali-Beh
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Patent number: 6867063Abstract: A method of manufacturing a semiconductor. A conventional bottom anti-reflective coating is applied over a reflective surface, for example an inter-layer dielectric. A second anti-reflective coating is deposited over the first anti-reflective coating. The second anti-reflective coating is organic and may be deposited through a spin-on process. The organic anti-reflective coating may be deposited with more exacting optical properties and better control of the layer thickness than conventional bottom anti-reflective coatings applied via chemical vapor deposition processes. The combination of the two layers of anti-reflective materials, the materials having differing optical properties, demonstrates superior control of reflections from underlying materials compared with conventional art methods. More particularly, an organic anti-reflective coating in conjunction with an inorganic anti-reflective coating may cancel reflections across a wide range of thicknesses in an underlying dielectric layer.Type: GrantFiled: September 30, 2002Date of Patent: March 15, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Kouros Ghandehari, Dawn Hopper, Wenmei Li, Angela T. Hui