Patents by Inventor Kourosh Gharachorloo

Kourosh Gharachorloo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10257208
    Abstract: A system and method for verifying content on a network site is provided. A document such as a website is identified. The document is accessed over a network from a content provider system connected to the network to obtain information about the document. Through an automated process, using the information about the document to determine whether the document conforms to one or more predetermined rules associated with the content provider system governing the usage of content in the document.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: April 9, 2019
    Assignee: Google LLC
    Inventors: Victor Bennett, Shrish Agrawal, Niels Provos, Jayesh Sharma, Kourosh Gharachorloo, Gokul Rajaram
  • Patent number: 8762280
    Abstract: A system and method for verifying content on a network site is provided. A document such as a website is identified. The document is accessed over a network from a content provider system connected to the network to obtain information about the document. Through an automated process, using the information about the document to determine whether the document conforms to one or more predetermined rules associated with the content provider system governing the usage of content in the document.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: June 24, 2014
    Assignee: Google Inc.
    Inventors: Victor Bennett, Shrish Agrawal, Niels Provos, Jayesh Sharma, Kourosh Gharachorloo, Gokul Rajaram
  • Patent number: 7523016
    Abstract: In general, systems and methods for identifying anomalous activity are described. For example, systems and methods are described, in which patterns of unusual behavior can be identified by aggregating logged, or sampled, data into cells and annotating each cell with statistically derived measures of how extreme the cell is relative to, for example, historical behavior of corresponding characteristics or relative to, for example, behavior of characteristics from a general population. Cells that have more than a predefined number of such annotations can be identified as anomalous and can be investigated by a user or outright acted upon in an automatic, pre-defined way.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: April 21, 2009
    Assignee: Google Inc.
    Inventors: Razvan Surdulescu, Kourosh Gharachorloo
  • Patent number: 7502895
    Abstract: Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate unnecessary snoops of the plurality of buses, and further configured to track requests from the one or more processors only if tracking the request does not result in a castout penalty.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: March 10, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Phillip Matthew Jones, Kourosh Gharachorloo
  • Patent number: 7467131
    Abstract: When searching a document database in response to a search query, a determination is made as to whether a query result corresponding to the search query is stored in a cache. When the query result is stored in the cache, a reuse count for the search query is accessed. When predefined conditions are satisfied, such as the reuse count being larger than a predetermined threshold count, an improved search result is generated in accordance with a first set of predetermined searching criteria, and at least a subset of the improved search result is returned.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: December 16, 2008
    Assignee: Google Inc.
    Inventors: Kourosh Gharachorloo, Fay Wen Chang, Deborah Anne Wallach
  • Patent number: 7389389
    Abstract: A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: June 17, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz A. Barroso, Robert J. Stets, Jr., Mosur K. Ravishankar, Andreas Nowatzyk
  • Patent number: 7254580
    Abstract: When a search query is received, a plurality of partition indexes are searched using the set of search terms in the search query. Each partition index corresponds to a partition of a document index. The search of each respective partition index identifies a subset of a plurality of document index sub-partitions corresponding to the respective partition index. Next, the search query is executed by only those document index sub-partitions identified by the subsets, thereby identifying documents that satisfy the search query. By using the partition index to reduce the number of document index sub-partitions searched while executing a search query, the execution of the search query is made more efficient.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 7, 2007
    Assignee: Google Inc.
    Inventors: Kourosh Gharachorloo, Fay Wen Chang, Deborah Anne Wallach, Sanjay Ghemawat, Jeffrey Dean
  • Publication number: 20070061520
    Abstract: Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 15, 2007
    Inventors: Phillip Jones, Kourosh Gharachorloo
  • Patent number: 7174346
    Abstract: Once a search query is received from a user, a standard index is searched based on the search query. The standard index forms part of a set of replicated standard indexes having multiple instances of the standard index. A signal is then determined based on the search of the standard index. When the received signal meets predefined criteria, an extended index is searched. The extended index forms part of a set of extended indexes having at least one instance of the extended index. There are fewer instances of the extended index than instances of the standard index. Extended search results are then obtained from the extended index and at least a portion of the extended search results is transmitted towards a user.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 6, 2007
    Assignee: Google, Inc.
    Inventors: Kourosh Gharachorloo, Fay Wen Chang, Deborah Anne Wallach, Sanjay Ghemawat, Jeffrey Dean
  • Patent number: 7152191
    Abstract: A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: December 19, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard E. Kessler, Peter J. Bannon, Kourosh Gharachorloo, Thukalan V. Verghese
  • Patent number: 6988170
    Abstract: A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: January 17, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk
  • Patent number: 6925537
    Abstract: A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: August 2, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Mosur K. Ravishankar, Robert J. Stets, Jr.
  • Patent number: 6918015
    Abstract: A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the distributed multiprocessing computer system is identified as a Home processor for a memory block if it includes the original memory block and a coherence directory for the memory block in its main memory. An Owner processor is another processor in the multiprocessing computer system that includes a copy of the Home processor memory block in a cache connected to its main memory. Whenever an Owner processor is present for a memory block, it is the only processor in the distributed multiprocessing computer system to contain a copy of the Home processor memory block.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: July 12, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard E. Kessler, Kourosh Gharachorloo, David H. Asher
  • Patent number: 6912624
    Abstract: To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: June 28, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk
  • Publication number: 20040260879
    Abstract: To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication.
    Type: Application
    Filed: February 2, 2004
    Publication date: December 23, 2004
    Inventors: Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk
  • Publication number: 20040148472
    Abstract: A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.
    Type: Application
    Filed: October 31, 2003
    Publication date: July 29, 2004
    Inventors: Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Mosur K. Ravishankar, Robert J. Stets
  • Patent number: 6751720
    Abstract: L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (“Dtags”) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: June 15, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert J. Stets, Jr., Mosur Kumaraswamy Ravishankar
  • Patent number: 6751710
    Abstract: The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using efficient cache coherence logic and methodologies. More specifically, the present invention is a system and method including a plurality of processor nodes configured to execute a cache coherence protocol that avoids the use of negative acknowledgment messages (NAKs) and ordering requirements on the underlying transaction-message interconnect/network and services most 3-hop transactions with only a single visit to the home node.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: June 15, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz A. Barroso, Mosur K. Ravishankar, Robert J. Stets, Jr., Daniel J. Scales
  • Patent number: 6748498
    Abstract: A system including a plurality of processor nodes is configured to execute a cache coherence protocol that avoids the use of negative acknowledgments and ordering requirements on the underlying transaction-message interconnect/network, and implements store-conditional memory transactions. A store-conditional memory transaction succeeds if a directory tracking the state of a memory line of information unambiguously indicates that the requesting node is the exclusive owner of the memory line, if the directory ambiguously indicates that the requesting node is sharing the memory line and the requesting node is in fact sharing the memory line, or if the directory unambiguously indicates that the requesting node is sharing the memory line.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: June 8, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz Andre Barroso, Mosur K. Ravishankar, Robert J. Stets, Daniel J. Scales
  • Patent number: 6738868
    Abstract: A system of scalable shared-memory multiprocessors includes processor nodes and I/O nodes. The I/O nodes connect I/O devices directly to an interconnection network of a system of scalable shared-memory multiprocessors. Each node of the system includes an interface to a local memory subsystem, a memory cache and a protocol engine. The local memory subsystem stores memory lines of information and a directory. Each entry in the directory stores sharing information concerning a memory line of information stored in the local memory subsystem. The protocol engine in each I/O node is configured to limit to a predefined period of time any sharing of a memory line of information from the memory subsystem of any other node. The protocol engine in the home node of the memory line is configured to identify only nodes other than I/O nodes that are sharing the memory line of information.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: May 18, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz Andre Barroso, Daniel J. Scales