Patents by Inventor Kourosh Gharachorloo

Kourosh Gharachorloo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040088487
    Abstract: A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads.
    Type: Application
    Filed: October 24, 2003
    Publication date: May 6, 2004
    Inventors: Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk
  • Publication number: 20040088523
    Abstract: A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.
    Type: Application
    Filed: October 23, 2003
    Publication date: May 6, 2004
    Inventors: Richard E. Kessler, Peter J. Bannon, Kourosh Gharachorloo, Thukalan V. Verghese
  • Patent number: 6725343
    Abstract: Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in another node. The cache memory system stores copies of memory lines and cache state information indicating whether the cached copy of each memory line is an exclusive copy. The logic of each respective node is configured to respond to a transaction request for a particular memory line and its corresponding directory entry, where the respective node is the home node of the particular memory.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: April 20, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk
  • Patent number: 6725334
    Abstract: To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: April 20, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk
  • Publication number: 20040064653
    Abstract: A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes.
    Type: Application
    Filed: September 26, 2003
    Publication date: April 1, 2004
    Inventors: Kourosh Gharachorloo, Luiz A. Barroso, Robert J. Stets, Mosur K. Ravishankar, Andreas Nowatzyk
  • Patent number: 6697919
    Abstract: A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: February 24, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz A. Barroso, Robert J. Stets, Jr., Mosur K. Ravishankar, Andreas Nowatzyk
  • Patent number: 6678840
    Abstract: A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: January 13, 2004
    Assignee: Hewlett-Packard Development Company, LP.
    Inventors: Richard E. Kessler, Peter J. Bannon, Kourosh Gharachorloo, Thukalan V. Verghese
  • Patent number: 6675265
    Abstract: A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: January 6, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Mosur K. Ravishankar, Robert J. Stets, Jr.
  • Patent number: 6668308
    Abstract: A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: December 23, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk
  • Patent number: 6640287
    Abstract: An invalid-to-dirty request permits a transition from an invalid memory state to a dirty state without requiring an up-to-date copy of the memory. The present invention is a system for supporting invalid-to-dirty memory transactions in an aggressive cache coherence protocol that minimizes directory entry locking. The nodes of a multiprocessor system each include a protocol engine that is configured to implement a distinct invalidation request that corresponds to an invalid-to-dirty memory transaction. If node O receives this distinct invalidation request while waiting for a response to an outstanding request for exclusive ownership, the protocol engine of node O is configured to treat the distinct invalidation request as applying to the memory line of information that is the subject of the outstanding request for exclusive ownership.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: October 28, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz Andre Barroso, Mosur Kumaraswamy Ravishankar, Robert J. Stets, Daniel J. Scales
  • Patent number: 6636949
    Abstract: In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol is responsible for cache coherence management across chip multiprocessor nodes, and is implemented by separate cache coherence protocol engines. The cache controller and the protocol engine within each node communicate and synchronize memory transactions involving multiple nodes to maintain cache coherence within and across the nodes. The present invention addresses race conditions that arise during this communication and synchronization.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: October 21, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert J. Stets, Mosur K. Ravishankar
  • Publication number: 20030196047
    Abstract: A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the distributed multiprocessing computer system is identified as a Home processor for a memory block if it includes the original memory block and a coherence directory for the memory block in its main memory. An Owner processor is another processor in the multiprocessing computer system that includes a copy of the Home processor memory block in a cache connected to its main memory. Whenever an Owner processor is present for a memory block, it is the only processor in the distributed multiprocessing computer system to contain a copy of the Home processor memory block.
    Type: Application
    Filed: March 31, 2003
    Publication date: October 16, 2003
    Inventors: Richard E. Kessler, Kourosh Gharachorloo, David H. Asher
  • Patent number: 6633960
    Abstract: A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the distributed multiprocessing computer system is identified as a Home processor for a memory block if it includes the original memory block and a coherence directory for the memory block in its main memory. An Owner processor is another processor in the multiprocessing computer system that includes a copy of the Home processor memory block in a cache connected to its main memory. Whenever an Owner processor is present for a memory block, it is the only processor in the distributed multiprocessing computer system to contain a copy of the Home processor memory block.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: October 14, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard E. Kessler, Kourosh Gharachorloo, David H. Asher
  • Patent number: 6622217
    Abstract: The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: September 16, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz A. Barroso, Mosur K. Ravishankar, Robert J Stets, Jr., Andreas Nowatzyk
  • Patent number: 6622218
    Abstract: The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions. Moreover, the protocol engine is configured to transition from one memory transaction to another in a minimum number of clock cycles.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: September 16, 2003
    Assignee: Hewlett-Packard Development Company, LP.
    Inventors: Kourosh Gharachorloo, Luiz A. Barroso, Mosur K. Ravishankar, Robert J. Stets
  • Publication number: 20030023814
    Abstract: L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (“Dtags”) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.
    Type: Application
    Filed: January 7, 2002
    Publication date: January 30, 2003
    Inventors: Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert J. Stets, Mosur Kumaraswamy Ravishankar
  • Publication number: 20020129208
    Abstract: In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol is responsible for cache coherence management across chip multiprocessor nodes, and is implemented by separate cache coherence protocol engines. The cache controller and the protocol engine within each node communicate and synchronize memory transactions involving multiple nodes to maintain cache coherence within and across the nodes. The present invention addresses race conditions that arise during this communication and synchronization.
    Type: Application
    Filed: January 7, 2002
    Publication date: September 12, 2002
    Applicant: Compaq Information Technologies, Group, L.P.
    Inventors: Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert J. Stets, Mosur K. Ravishankar
  • Publication number: 20020124144
    Abstract: A system including a plurality of processor nodes is configured to execute a cache coherence protocol that avoids the use of negative acknowledgments and ordering requirements on the underlying transaction-message interconnect/network, and implements store-conditional memory transactions. A store-conditional memory transaction succeeds if a directory tracking the state of a memory line of information unambiguously indicates that the requesting node is the exclusive owner of the memory line, if the directory ambiguously indicates that the requesting node is sharing the memory line and the requesting node is in fact sharing the memory line, or if the directory unambiguously indicates that the requesting node is sharing the memory line.
    Type: Application
    Filed: January 7, 2002
    Publication date: September 5, 2002
    Inventors: Kourosh Gharachorloo, Luiz Andre Barroso, Mosur K. Ravishankar, Robert J. Stets, Daniel J. Scales
  • Publication number: 20020124143
    Abstract: Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in another node. The cache memory system stores copies of memory lines and cache state information indicating whether the cached copy of each memory line is an exclusive copy. The logic of each respective node is configured to respond to a transaction request for a particular memory line and its corresponding directory entry, where the respective node is the home node of the particular memory.
    Type: Application
    Filed: October 5, 2001
    Publication date: September 5, 2002
    Applicant: Compaq Information Technologies Group, L.P.
    Inventors: Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk
  • Publication number: 20020087806
    Abstract: The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions. Moreover, the protocol engine is configured to transition from one memory transaction to another in a minimum number of clock cycles.
    Type: Application
    Filed: January 7, 2002
    Publication date: July 4, 2002
    Inventors: Kourosh Gharachorloo, Luiz A. Barroso, Mosur K. Ravishankar, Robert J. Stets