Patents by Inventor Koushik Banerjee

Koushik Banerjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210225444
    Abstract: An apparatus is described. The apparatus includes a cross-point non volatile memory cell array comprised of a first plurality of access lines and a second orthogonal plurality of access lines. Each of the first plurality of access lines are coupled to a first address decoder through a respective pass transistor. The pass transistor is coupled to control circuitry to bias the pass transistor into one of at least two states that include a first active state determined from a second address decoder and a second active state determined from the second address decoder.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Inventors: Koushik BANERJEE, Sanjay RANGAN
  • Patent number: 10884640
    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
  • Patent number: 10796761
    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan
  • Publication number: 20200211032
    Abstract: A tamperproof, counterfeiting resistant security label is envisaged. The security label includes a base layer, an adhesive layer applied atop the base layer, and a face stock positioned above the adhesive layer. The face stock essentially includes at least one scannable security element disposed thereon. The security element comprises an indicium positioned within the periphery of the face stock. The indicium is oriented with reference to the positioning of an invisible reference point situated within the periphery of the security label. The reference point, given its programmatic conceptualization and positioning is rendered invisible to naked human eye as well as to conventional scanning devices which have not been specifically pre-programmed to scan and identify otherwise invisible reference points. Positioning of the reference point and the positioning of the indicium put together forms a non-apparent, signature unique to the security label.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 2, 2020
    Inventor: KOUSHIK BANERJEE
  • Patent number: 10553286
    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming pulse with the one or more selected timing offset to program the memory cell within the array of memory cells.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Daniel Chu, Shravya Gottipati
  • Publication number: 20190348114
    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 14, 2019
    Applicant: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan
  • Publication number: 20190324671
    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
    Type: Application
    Filed: April 2, 2019
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
  • Patent number: 10360977
    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan
  • Publication number: 20190206491
    Abstract: Examples may include techniques to mitigate voltage threshold drift over a period of time that may cause selection failure for selecting memory cells of a memory device. A snap-back event detection is used to determine whether a selected memory cell has been selected for at least a first refresh write operation using one or more selection bias voltages. A subsequent refresh write operation may be implemented based on this determination.
    Type: Application
    Filed: March 7, 2019
    Publication date: July 4, 2019
    Inventor: Koushik BANERJEE
  • Publication number: 20190102099
    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: INTEL CORPORATION
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
  • Patent number: 10248351
    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
  • Publication number: 20190043585
    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming pulse with the one or more selected timing offset to program the memory cell within the array of memory cells.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Koushik Banerjee, Daniel Chu, Shravya Gottipati
  • Publication number: 20190043576
    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan
  • Patent number: 7045890
    Abstract: A heat spreader and stiffener device has a stiffener portion extending towards a center of the heat spreader and stiffener device and mountable to a die-side surface of a substrate.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: May 16, 2006
    Assignee: Intel Corporation
    Inventors: Hong Xie, Kristopher Frutschy, Koushik Banerjee, Ajit Sathe
  • Publication number: 20030062618
    Abstract: Arrangements are used to increase the structural rigidity of a semiconductor package.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Hong Xie, Kristopher Frutschy, Koushik Banerjee, Ajit Sathe
  • Patent number: 6459563
    Abstract: An electronic package which has a polygonal shaped heat slug. The heat slug extends from a top surface of a package which has a plurality of vias. The package also has a number of capacitors that are mounted to the top surface. Some of the capacitors are located between the heat slug and the vias. The polygonal shape of the heat slug provides additional space on the top surface so that capacitors can be added without eliminating vias from the package.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: October 1, 2002
    Assignee: Intel Corporation
    Inventors: Robert J. Chroneos, Jr., Koushik Banerjee
  • Patent number: 6440770
    Abstract: An integrated circuit package. The package includes a substrate that has a first internal conductive bus and a second internal conductive bus that are located on a common layer of the substrate and dedicated to different power voltage levels. The busses are coupled to external lands located on a first surface of the package by vias that extend through the substrate. The first and second busses are located on a common layer of the substrate. The package contains an integrated circuit which is mounted to a heat slug that is attached to a second surface of the package. The integrated circuit is coupled to bond fingers located on a shelf of the substrate. Some of the bond fingers are connected to the internal busses by conductive strips that wrap around the edges of the shelf. Some of the vias are connected to a whole group of external lands. Grouping the lands to a single via reduces the number of vias on the second surface of the package.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: August 27, 2002
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Robert J. Chroneos, Jr., Tom Mozdzen
  • Patent number: 6403891
    Abstract: A printed circuit board which has an ink block and a first conductive layer that are attached to a solder mask. A first dielectric layer is attached to the first conductive layer. Indicia is formed in the ink block by a laser ablation process. The first conductive layer has a first non-metallized area located beneath the ink block. Eliminating metal beneath the ink block would reduce the amount of energy that is absorbed by the circuit board during the laser ablation process. The printed circuit board has multiple layers of conductive and dielectric material. Some or all of the conductive layers may have non-metallized areas located beneath the ink block.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: June 11, 2002
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Craig Randleman
  • Publication number: 20020023766
    Abstract: An electronic package which has a polygonal shaped heat slug. The heat slug extends from a top surface of a package which has a plurality of vias. The package also has a number of capacitors that are mounted to the top surface. Some of the capacitors are located between the heat slug and the vias. The polygonal shape of the heat slug provides additional space on the top surface so that capacitors can be added without eliminating vias from the package.
    Type: Application
    Filed: April 25, 2001
    Publication date: February 28, 2002
    Inventors: Robert J. Chroneos, Koushik Banerjee
  • Patent number: 6256189
    Abstract: An electronic package which has a polygonal shaped heat slug. The heat slug extends from a top surface of a package which has a plurality of vias. The package also has a number of capacitors that are mounted to the top surface. Some of the capacitors are located between the heat slug and the vias. The polygonal shape of the heat slug provides additional space on the top surface so that capacitors can be added without eliminating vias from the package.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: July 3, 2001
    Assignee: Intel Corporation
    Inventors: Robert J. Chroneos, Jr., Koushik Banerjee