Patents by Inventor Koushik Banerjee

Koushik Banerjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6403891
    Abstract: A printed circuit board which has an ink block and a first conductive layer that are attached to a solder mask. A first dielectric layer is attached to the first conductive layer. Indicia is formed in the ink block by a laser ablation process. The first conductive layer has a first non-metallized area located beneath the ink block. Eliminating metal beneath the ink block would reduce the amount of energy that is absorbed by the circuit board during the laser ablation process. The printed circuit board has multiple layers of conductive and dielectric material. Some or all of the conductive layers may have non-metallized areas located beneath the ink block.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: June 11, 2002
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Craig Randleman
  • Publication number: 20020023766
    Abstract: An electronic package which has a polygonal shaped heat slug. The heat slug extends from a top surface of a package which has a plurality of vias. The package also has a number of capacitors that are mounted to the top surface. Some of the capacitors are located between the heat slug and the vias. The polygonal shape of the heat slug provides additional space on the top surface so that capacitors can be added without eliminating vias from the package.
    Type: Application
    Filed: April 25, 2001
    Publication date: February 28, 2002
    Inventors: Robert J. Chroneos, Koushik Banerjee
  • Patent number: 6256189
    Abstract: An electronic package which has a polygonal shaped heat slug. The heat slug extends from a top surface of a package which has a plurality of vias. The package also has a number of capacitors that are mounted to the top surface. Some of the capacitors are located between the heat slug and the vias. The polygonal shape of the heat slug provides additional space on the top surface so that capacitors can be added without eliminating vias from the package.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: July 3, 2001
    Assignee: Intel Corporation
    Inventors: Robert J. Chroneos, Jr., Koushik Banerjee
  • Patent number: 6214638
    Abstract: An integrated circuit package which has a staggered bond wire pattern that increases the bond finger width to pad pitch ratio of the package. The package includes a first bond shelf, a second bond shelf and a third bond shelf. Mounted to the package is an integrated circuit which has a plurality of die pads. The die pads are arranged in a pattern of groups, wherein each group has a first die pad that is adjacent to a second die pad, and a third die pad that is adjacent to the second die pad and a first die pad of an adjacent group. Bond wires connect the first die pads to the first bond shelf, the second die pads to the second bond shelf and the third die pads to the third bond shelf, so that each adjacent die pad is connected to a different bond shelf. The staggered bond pattern maximizes the bond finger width of the package.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: April 10, 2001
    Assignee: Intle Corporation
    Inventor: Koushik Banerjee
  • Patent number: 6043559
    Abstract: An integrated circuit package. The package includes a substrate that has a first internal conductive bus and a second internal conductive bus that are located on a common layer of the substrate and dedicated to different power voltage levels. The busses are coupled to external lands located on a first surface of the package by vias that extend through the substrate. The first and second busses are located on a common layer of the substrate. The package contains an integrated circuit which is mounted to a heat slug that is attached to a second surface of the package. The integrated circuit is coupled to bond fingers located on a shelf of the substrate. Some of the bond fingers are connected to the internal busses by conductive strips that wrap around the edges of the shelf. Some of the vias are connected to a whole group of external lands. Grouping the lands to a single via reduces the number of vias on the second surface of the package.
    Type: Grant
    Filed: September 9, 1996
    Date of Patent: March 28, 2000
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Robert J. Chroneos, Jr., Tom Mozdzen
  • Patent number: 6031283
    Abstract: An integrated circuit package which contains an integrated circuit. The internal integrated circuit is coupled to external lands located on a first outer surface of the package by a plurality of vias. The vias extend through the package from the first outer surface to an opposite second outer surface. The package has a plurality of devices such as capacitors that are mounted to the second outer surface. Some of the vias are connected to a whole group of external lands. Grouping the lands to a single via reduces the number of vias on the second surface of the package. The reduction in vias allows additional capacitors to be mounted to the second surface of the package.
    Type: Grant
    Filed: September 9, 1996
    Date of Patent: February 29, 2000
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Robert J. Chroneos, Jr., Tom Mozdzen
  • Patent number: 5895977
    Abstract: An integrated circuit package which has a staggered bond wire pattern that increases the bond finger width to pad pitch ratio of the package. The package includes a first bond shelf, a second bond shelf and a third bond shelf. Mounted to the package is an integrated circuit which has a plurality of die pads. The die pads are arranged in a pattern of groups, wherein each group has a first die pad that is adjacent to a second die pad, and a third die pad that is adjacent to the second die pad and a first die pad of an adjacent group. Bond wires connect the first die pads to the first bond shelf, the second die pads to the second bond shelf and the third die pads to the third bond shelf, so that each adjacent die pad is connected to a different bond shelf. The staggered bond pattern maximizes the bond finger width of the package.
    Type: Grant
    Filed: August 8, 1996
    Date of Patent: April 20, 1999
    Assignee: Intel Corporation
    Inventor: Koushik Banerjee
  • Patent number: 5811880
    Abstract: An electronic package which contains discrete resistive and capacitive components used to control the operating device of an integrated circuit located within the package. The package has a bonding shelf that has a plurality of bond fingers which are connected to the integrated circuit. The discrete passive components are mounted to the bonding shelf and connected to the bond fingers by lead traces. The lead traces terminate at the discrete devices so that the resistor and capacitor cannot be accessed through the external contacts of the package. The integrated circuit and discrete components are typically enclosed by a molded plastic material to prevent physical access to the devices without damaging the package.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: September 22, 1998
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Barbara Jane Ultis, Sanjay Gupta, John F. McMahon
  • Patent number: 5787575
    Abstract: A method for plating an integrated circuit package. The method includes constructing a package which has a plurality of internal bond fingers that are subsequently coupled to an integrated circuit. The package contains a plurality of vias that are electrically connected to the bond fingers. The vias are also coupled to a layer of metallization that extends across an outer surface of the package. The meallization layer is used as a plating bar to plate the internal bond fingers. After plating the meallization layer is etched from the surface of the package.
    Type: Grant
    Filed: September 9, 1996
    Date of Patent: August 4, 1998
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Robert J. Chroneos, Jr., Tom Mozdzen
  • Patent number: 5734559
    Abstract: An integrated circuit package which has a plurality of bond fingers arranged in a staggered row arrangement on a bond shelf of the package. The bond shelf contains a first row of bond fingers that are separated by a plurality of spaces. The bond shelf also has a second row of bond fingers which each have a bond pad and a lead trace that extends through the spaces of the first row of bond fingers.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: March 31, 1998
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Robert J. Chroneos, Jr.
  • Patent number: 5557502
    Abstract: An integrated circuit package which has internal bonding pads that are located on bonding shelves and coupled to internal conductive power/ground planes by conductive strips that extend along the edges of the shelves. The edge strips eliminate the need for conventional vias to couple the bonding pads to the planes and thus reduce the cost and size of the package and improve package electrical performance (less inductive, less resistance path). The bonding pads are coupled to an integrated circuit that is mounted to a heat slug attached to a top surface of the package. The heat slug can function as both a ground path and a thermal sink for the integrated circuit. The package may have capacitors coupled to the internal routing of the package to reduce the electrical noise of the signals provided to the integrated circuit. Additionally, the package may have multiple power planes dedicated to different voltage levels.
    Type: Grant
    Filed: March 2, 1995
    Date of Patent: September 17, 1996
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Debendra Mallik, Ashok Seth
  • Patent number: 5444602
    Abstract: An electronic package which has a heat sink that is attached to the lead frame of the package with a material that is both electrically and thermally conductive. The lead frame is also coupled to a first surface of an integrated circuit die with tape automated bonded (TAB) leads. The low thermal resistance of the heat sink increases the thermal performance of the package. The heat sink may also be mounted directly to the die with a conductive material so that the die is electrically grounded to the heat sink. The heat sink is then bonded to the leads of the lead frame that are dedicated to ground. In this embodiment, the heat sink provides the dual functions of a ground plate and a heat spreader.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: August 22, 1995
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Siva Natarajan, Debendra Mallik, Praveen Jain
  • Patent number: 5345363
    Abstract: An integrated circuit package which utilizes a standard TAB tape that can couple a lead frame to one of a number of integrated circuit dies that have different outer dimensions. The TAB tape includes a sheet of polyimide which supports a plurality of conductive leads. The sheet has a rectangular center opening which provides clearance for the IC die. Adjacent to each edge of the center opening are a plurality of equally spaced contact openings which expose portions of the leads. The leads are coupled to the integrated circuit by attaching the contact portions to the surface pads of the die. The contact openings are located at various distances from the center opening so that the tape can accommodate different die sizes. The leads of the TAB tape are also attached to a lead frame through lead frame openings in the polyimide.
    Type: Grant
    Filed: April 7, 1993
    Date of Patent: September 6, 1994
    Assignee: Intel Corporation
    Inventors: Bidyut Bhattacharyya, Koushik Banerjee