Patents by Inventor Kouta Noda

Kouta Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956580
    Abstract: A microphone assembly comprises a circuit board, a microphone element connected to the circuit board, an external connection interface connected to the circuit board, and hot melt that is formed to cover the circuit board, the microphone element, and the external connection interface and has a hole formed to expose a part of the back side of the circuit board or the sound receiving part of the microphone element.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: April 9, 2024
    Assignee: HOSIDEN CORPORATION
    Inventors: Shunji Muraoka, Shushin Noda, Yoshifumi Yamanaka, Kouta Onoyama, Daisuke Kitaguchi, Jun Miyajima
  • Publication number: 20120125680
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Application
    Filed: January 25, 2012
    Publication date: May 24, 2012
    Applicant: IBIDEN CO., LTD
    Inventors: Naohiro Hirose, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Patent number: 8148643
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: April 3, 2012
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Patent number: 8065794
    Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: November 29, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Honchin En, Tohru Nakai, Takeo Oki, Naohiro Hirose, Kouta Noda
  • Patent number: 8021748
    Abstract: A printed wiring board is provided which includes an interlayer dielectric layer formed on a substrate from a curable resin having flaky particles dispersed therein. The printed wiring board is excellent in cooling/heating cycle resistance and packaging reliability while maintaining a satisfactory heat resistance, electrical insulation, heat liberation, connection reliability and chemical stability. Also a method of producing a printed wiring board is proposed in which an imprint method using a mold having formed thereon convexities corresponding to wiring patterns and viaholes to be formed being buried in an interlayer dielectric layer is used to form the wiring patterns and viaholes by transcribing the concavities of the mold to the interlayer dielectric layer. The imprint method permits to form the wiring patterns and viaholes but assures an easy and accurate transcription without any optical transcription or complicated etching.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: September 20, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Kouta Noda, Yasushi Inagaki
  • Patent number: 7832098
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: November 16, 2010
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Patent number: 7827680
    Abstract: An electroplating process of electroplating an electrically conductive substrate is described. The process includes electroplating intermittently to a predetermined plating thickness using the substrate surface as a cathode and a plating metal as an anode at a constant voltage between the anode and the cathode by repeating application of a voltage between a cathode and an anode and interruption of the application alternately. It is described that a voltage time/interruption time ratio is 0.1 to 1.0, a voltage time is not longer than 10 seconds, and an interruption time is not less than 1 x 10-12 seconds.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: November 9, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Honchin En, Tohru Nakai, Takeo Oki, Naohiro Hirose, Kouta Noda
  • Patent number: 7691189
    Abstract: The present invention is directed to a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity, and by which uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: April 6, 2010
    Assignee: Ibiden Co., Ltd.
    Inventors: Honchin En, Tohru Nakai, Takeo Oki, Naohiro Hirose, Kouta Noda
  • Publication number: 20090145652
    Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.
    Type: Application
    Filed: September 26, 2008
    Publication date: June 11, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Honchin En, Tohru Nakai, Takeo Oki, Naohiro Hirose, Kouta Noda
  • Patent number: 7415761
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: August 26, 2008
    Assignee: IBIDEN Co., Ltd.
    Inventors: Naohiro Hirose, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Publication number: 20080189943
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Application
    Filed: April 7, 2008
    Publication date: August 14, 2008
    Applicant: IBIDEN CO., LTD.
    Inventors: Naohiro HIROSE, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Publication number: 20080173473
    Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 ?m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.
    Type: Application
    Filed: October 19, 2007
    Publication date: July 24, 2008
    Applicant: IBIDEN CO., LTD
    Inventors: Naohiro HIROSE, Kouta Noda, Hiroshi Segawa, Honjin En, Kiyotaka Tsukada, Naoto Ishida, Kouji Asano, Atsushi Shouda
  • Publication number: 20080023815
    Abstract: A printed wiring board including a substrate, conductor circuits and interlayer dielectric layers stacked alternately on the substrate, each of the interlayer dielectric layers including a curable resin having flaky particles dispersed therein, and viaholes formed in the interlayer dielectric layers and electrically connecting the conductor circuits at different levels.
    Type: Application
    Filed: September 21, 2007
    Publication date: January 31, 2008
    Applicant: IBIDEN CO., LTD.
    Inventors: Motoo ASAI, Kouta Noda, Yasushi Inagaki
  • Publication number: 20080014336
    Abstract: A method of forming a multilayer printed wiring board including forming a yet-to-cure interlayer dielectric layer by applying or attaching, to a dielectric substrate, an interlayer dielectric material of liquid or dry film including one or more of thermosetting resin, mixture of thermosetting and thermoplastic resins, photosensitized thermosetting resin, mixture of photosensitized thermosetting and thermoplastic resins, and photosensitive resin, softening the dielectric layer, pressing mold having convexities onto the softened dielectric layer to form concavities for conductor and concavities or through-holes for viaholes, cooling or heating the softened dielectric layer to temperature at which shapes of the concavities and/or through-holes in the dielectric layer are maintained, removing the mold from the dielectric layer, heating, or irradiating ultraviolet rays to, the dielectric layer, and curing, by heating, the dielectric layer, and forming the circuits and viaholes by forming a conductive material in t
    Type: Application
    Filed: September 21, 2007
    Publication date: January 17, 2008
    Applicant: IBIDEN CO., LTD.
    Inventors: Motoo ASAI, Kouta Noda, Yasushi Inagaki
  • Publication number: 20070266886
    Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.
    Type: Application
    Filed: April 17, 2007
    Publication date: November 22, 2007
    Inventors: Honchin En, Tohru Nakai, Takeo Oki, Naohiro Hirose, Kouta Noda
  • Patent number: 7230188
    Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: June 12, 2007
    Assignee: Ibiden Co., Ltd.
    Inventors: Honchin En, Tohru Nakai, Takeo Oki, Naohiro Hirose, Kouta Noda
  • Publication number: 20070013049
    Abstract: A printed wiring board is provided which includes an interlayer dielectric layer formed on a substrate from a curable resin having flaky particles dispersed therein. The printed wiring board is excellent in cooling/heating cycle resistance and packaging reliability while maintaining a satisfactory heat resistance, electrical insulation, heat liberation, connection reliability and chemical stability. Also a method of producing a printed wiring board is proposed in which an imprint method using a mold having formed thereon convexities corresponding to wiring patterns and viaholes to be formed being buried in an interlayer dielectric layer is used to form the wiring patterns and viaholes by transcribing the concavities of the mold to the interlayer dielectric layer. The imprint method permits to form the wiring patterns and viaholes but assures an easy and accurate transcription without any optical transcription or complicated etching.
    Type: Application
    Filed: September 29, 2004
    Publication date: January 18, 2007
    Applicant: IBIDEN CO., LTD.
    Inventors: Motoo Asai, Kouta Noda, Yasushi Inagaki
  • Publication number: 20040134682
    Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.
    Type: Application
    Filed: January 6, 2004
    Publication date: July 15, 2004
    Applicant: IBIDEN CO., LTD.
    Inventors: Honchin En, Tohru Nakai, Takeo Oki, Naohiro Hirose, Kouta Noda
  • Patent number: 6762921
    Abstract: This invention is to propose a technique of producing a printed wiring board having an excellent adhesion property between an electroless plated film and an electrolytic plated film constituting a conductor circuit through a semi-additive process without causing the peeling of a plating resist and is a printed wiring board comprising conductor circuits formed on a roughened surface of an insulating layer, in which the conductor circuit is constituted with an electroless plated film at the side of the insulating layer and an electrolytic plated film at the opposite side and the electroless plated film located at the side of the insulating layer is formed so as to follow to the roughened surface of the insulating layer. This printed wiring board is produced by a semi-additive method wherein the electroless plated film is formed on the roughened surface of the insulating layer so as to follow to the roughened surface of the insulating layer.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: July 13, 2004
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Kouta Noda, Takashi Kariya
  • Patent number: RE40947
    Abstract: A multilayer printed wiring board is composed of a substrate provided with through-holes, and a wiring board formed on the substrate through the interposition of an interlaminar insulating resin layer, the through-holes having a roughened internal surface and being filled with a filler, an exposed part of the filler in the through-holes being covered with a through-hole-covering conductor layer, and a viahole formed just thereabove being connected to the through-hole-covering conductor layer. Without peeling between the through-holes and the filler, this wiring board has a satisfactory connection reliability between the through-holes and the internal layer circuit and provides a high density wiring.
    Type: Grant
    Filed: October 12, 1990
    Date of Patent: October 27, 2009
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Kenichi Shimada, Kouta Noda, Takashi Kariya, Hiroshi Segawa