Patents by Inventor Koyo Katsura

Koyo Katsura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8332683
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Publication number: 20100180140
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Application
    Filed: March 25, 2010
    Publication date: July 15, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 7711976
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: May 4, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 7602389
    Abstract: A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: October 13, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
  • Publication number: 20080168295
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Application
    Filed: July 13, 2007
    Publication date: July 10, 2008
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 7333116
    Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: February 19, 2008
    Assignee: Renesas Technology Corporation
    Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
  • Patent number: 7254737
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: August 7, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 7142213
    Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: November 28, 2006
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Yasuhiro Nakatsuka, Keisuke Nakashima, Shigeru Matsuo, Masahisa Narita, Koyo Katsura, Hidehito Takewa, Tomoaki Aoki
  • Publication number: 20060202992
    Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.
    Type: Application
    Filed: May 12, 2006
    Publication date: September 14, 2006
    Inventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone
  • Publication number: 20060203000
    Abstract: A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
    Type: Application
    Filed: March 2, 2006
    Publication date: September 14, 2006
    Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
  • Patent number: 7082224
    Abstract: An apparatus for calculating a normalized correlation coefficient used as a similarity evaluation measure by using image data values of pixels in a template image and image data values of pixels in a subimage, included in a search image, corresponding to the template image, has a memory that stores image data values of pixels in the search image and calculating means that calculate a sum of image data values of pixels in the template image and a sum of image data values of pixels in the first rectangular region in the search image or a sum of squares of image data values of pixels in the template image and a sum of squares of image data values of pixels in the first rectangular region in the search image.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: July 25, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuji Ikeda, Syoji Yoshida, Keisuke Nakashima, Koyo Katsura, Shigeru Shibukawa, Haruo Yoda, Takashi Hotta
  • Patent number: 7064756
    Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: June 20, 2006
    Assignee: Renesas Technology Corporation
    Inventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone
  • Patent number: 7019751
    Abstract: A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: March 28, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
  • Patent number: 7006134
    Abstract: A pen type input device with a camera has improved usability as a result in improved construction of the device. The pen type input device with the camera is adapted for use in detecting both of a horizontally elongated object and a vertically elongated object. On the other hand, means for pointing to the object and the process content simultaneously, and further means for detecting the fact that the user is pointing to the object in an erroneous manner and for teaching a correct manner of pointing to the object depending thereon are provided.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: February 28, 2006
    Assignees: Hitachi, Ltd., Hitachi Via Mechanics, LTD
    Inventors: Toshifumi Arai, Kimiyoshi Machii, Koyo Katsura, Hideyuki Watanabe
  • Publication number: 20050264574
    Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
    Type: Application
    Filed: July 18, 2005
    Publication date: December 1, 2005
    Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
  • Patent number: 6954206
    Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: October 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
  • Publication number: 20050147305
    Abstract: An apparatus for calculating a normalized correlation coefficient used as a similarity evaluation measure by using image data values of pixels in a template image and image data values of pixels in a subimage, included in a search image, corresponding to the template image, has a memory that stores image data values of pixels in the search image and calculating means that calculate a sum of image data values of pixels in the template image and a sum of image data values of pixels in the first rectangular region in the search image or a sum of squares of image data values of pixels in the template image and a sum of squares of image data values of pixels in the first rectangular region in the search image.
    Type: Application
    Filed: February 18, 2005
    Publication date: July 7, 2005
    Inventors: Mitsuji Ikeda, Syoji Yoshida, Keisuke Nakashima, Koyo Katsura, Shigeru Shibukawa, Haruo Yoda, Takashi Hotta
  • Publication number: 20050041489
    Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.
    Type: Application
    Filed: September 23, 2004
    Publication date: February 24, 2005
    Applicant: RENESAS TECHNOLOGY CORPORATION
    Inventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone
  • Publication number: 20040263523
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Application
    Filed: July 23, 2004
    Publication date: December 30, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: RE39529
    Abstract: A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: March 27, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Koyo Katsura, Shinichi Kojima, Noriyuki Kurakami