Patents by Inventor Koyo Katsura
Koyo Katsura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8332683Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: GrantFiled: March 25, 2010Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Publication number: 20100180140Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: ApplicationFiled: March 25, 2010Publication date: July 15, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Patent number: 7711976Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: GrantFiled: July 13, 2007Date of Patent: May 4, 2010Assignee: Renesas Technology Corp.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Patent number: 7602389Abstract: A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.Type: GrantFiled: March 2, 2006Date of Patent: October 13, 2009Assignee: Hitachi, Ltd.Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
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Publication number: 20080168295Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: ApplicationFiled: July 13, 2007Publication date: July 10, 2008Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Patent number: 7333116Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.Type: GrantFiled: July 18, 2005Date of Patent: February 19, 2008Assignee: Renesas Technology CorporationInventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
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Patent number: 7254737Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: GrantFiled: July 23, 2004Date of Patent: August 7, 2007Assignee: Renesas Technology Corp.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Patent number: 7142213Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.Type: GrantFiled: April 13, 2004Date of Patent: November 28, 2006Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Yasuhiro Nakatsuka, Keisuke Nakashima, Shigeru Matsuo, Masahisa Narita, Koyo Katsura, Hidehito Takewa, Tomoaki Aoki
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Publication number: 20060203000Abstract: A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.Type: ApplicationFiled: March 2, 2006Publication date: September 14, 2006Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
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Publication number: 20060202992Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.Type: ApplicationFiled: May 12, 2006Publication date: September 14, 2006Inventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone
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Patent number: 7082224Abstract: An apparatus for calculating a normalized correlation coefficient used as a similarity evaluation measure by using image data values of pixels in a template image and image data values of pixels in a subimage, included in a search image, corresponding to the template image, has a memory that stores image data values of pixels in the search image and calculating means that calculate a sum of image data values of pixels in the template image and a sum of image data values of pixels in the first rectangular region in the search image or a sum of squares of image data values of pixels in the template image and a sum of squares of image data values of pixels in the first rectangular region in the search image.Type: GrantFiled: February 18, 2005Date of Patent: July 25, 2006Assignee: Hitachi, Ltd.Inventors: Mitsuji Ikeda, Syoji Yoshida, Keisuke Nakashima, Koyo Katsura, Shigeru Shibukawa, Haruo Yoda, Takashi Hotta
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Patent number: 7064756Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.Type: GrantFiled: September 23, 2004Date of Patent: June 20, 2006Assignee: Renesas Technology CorporationInventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone
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Patent number: 7019751Abstract: A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.Type: GrantFiled: August 8, 2003Date of Patent: March 28, 2006Assignee: Hitachi, Ltd.Inventors: Koyo Katsura, Yasushi Fukunaga, Ryo Fujita, Kazuyoshi Koga, Takehiko Nishida
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Patent number: 7006134Abstract: A pen type input device with a camera has improved usability as a result in improved construction of the device. The pen type input device with the camera is adapted for use in detecting both of a horizontally elongated object and a vertically elongated object. On the other hand, means for pointing to the object and the process content simultaneously, and further means for detecting the fact that the user is pointing to the object in an erroneous manner and for teaching a correct manner of pointing to the object depending thereon are provided.Type: GrantFiled: August 12, 1999Date of Patent: February 28, 2006Assignees: Hitachi, Ltd., Hitachi Via Mechanics, LTDInventors: Toshifumi Arai, Kimiyoshi Machii, Koyo Katsura, Hideyuki Watanabe
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Publication number: 20050264574Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.Type: ApplicationFiled: July 18, 2005Publication date: December 1, 2005Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
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Patent number: 6954206Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.Type: GrantFiled: September 25, 2003Date of Patent: October 11, 2005Assignee: Hitachi, Ltd.Inventors: Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka, Yasuhiro Nakatsuka
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Publication number: 20050147305Abstract: An apparatus for calculating a normalized correlation coefficient used as a similarity evaluation measure by using image data values of pixels in a template image and image data values of pixels in a subimage, included in a search image, corresponding to the template image, has a memory that stores image data values of pixels in the search image and calculating means that calculate a sum of image data values of pixels in the template image and a sum of image data values of pixels in the first rectangular region in the search image or a sum of squares of image data values of pixels in the template image and a sum of squares of image data values of pixels in the first rectangular region in the search image.Type: ApplicationFiled: February 18, 2005Publication date: July 7, 2005Inventors: Mitsuji Ikeda, Syoji Yoshida, Keisuke Nakashima, Koyo Katsura, Shigeru Shibukawa, Haruo Yoda, Takashi Hotta
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Publication number: 20050041489Abstract: In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.Type: ApplicationFiled: September 23, 2004Publication date: February 24, 2005Applicant: RENESAS TECHNOLOGY CORPORATIONInventors: Yasuhiro Nakatsuka, Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone
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Publication number: 20040263523Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.Type: ApplicationFiled: July 23, 2004Publication date: December 30, 2004Applicant: Hitachi, Ltd.Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
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Patent number: RE39529Abstract: A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.Type: GrantFiled: March 28, 2000Date of Patent: March 27, 2007Assignee: Renesas Technology Corp.Inventors: Koyo Katsura, Shinichi Kojima, Noriyuki Kurakami