Graphic processing apparatus utilizing improved data transfer to reduce memory size
A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.
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This is a continuation of Reissue application Ser. No. 07/985,141, filed Dec. 3, 1992 now U.S. Pat. No. RE37103.
BACKGROUND OF THE INVENTIONThe present invention relates to a graphic processing apparatus for processing graphic data stored in a memory, and in particular, to a graphic processing apparatus in which the number of memories to be employed can be reduced so as to minimize the size of the processing apparatus.
For example, the Japanese Patent Publication JP-A-60-136793 describes a graphic processing apparatus in which characters and graphic data are generated in a display memory (frame buffer) so as to be delivered to output devices such as a display and a printer. In this conventional example, a high-speed graphic drawing operation is achieved by use of a method in which data bits constituting at least one pixel are packed in a word so as to be stored in the memory. In contrast with the prior method in which information of a pixel requires a plurality of words, this method allows accessing of the memory in the unit of a word (16 bits); in consequence, by packing information of a pixel in a single word, at least one pixel can be updated through one access, which therefore increases the processing speed.
In the conventional example above, although the memory is connected to a 16-bit data bus, the dynamic random access memory (DRAM) generally possesses a 1-bit or 4-bit data bus, and hence at least four to 16 memory elements are required, which prevents the apparatus from being miniturized.
In addition, the Japanese Patent Publication JP-A-60-225888 describes an apparatus including a dynamic random access memory (DRAM) having a nibble function (one of consecutive data read functions); however, description has not been given of a combination with a graphic processor in which data are accessed in a parallel fashion.
Moreover, in the Japanese Patent Publication JP-A-55-129387, there is described a system for transferring serial data between a processor and an external device; however, parallel data access is carried out between the processor and a memory.
SUMMARY OF THE INVENTIONIt is therefore an object of the present invention to provide a small-sized graphic processing apparatus in which data transfer is enabled through a data bus having a reduced bit width so as to minimize the number of memory elements employed.
In order to achieve the object above, according to the present invention, there is disposed data converting means between processor means processing parallel data and a memory so as to enable the data bus width of the memory to be smaller than that of the processor means. The data converting means includes a latch for temporarily storing read data and a multiplexer for writing data. The present invention is characterized in that a memory having a successive data read function is applied to a processor effecting parallel data processing.
In the graphic processing apparatus according to the present invention, the memory is accessed in a time shared fashion such that data is converted by the converting means into parallel data. That is, in a data reading operation, data sequentially read out in a time shared fashion is temporarily stored in a latch so as to be supplied as parallel data to the processor. Moreover, in a data writing operation, parallel data supplied from the processor is sequentially written through the multiplexer into the memory in a time shared fashion.
The present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
Referring now to the drawings, description will be given of an embodiment according to the present invention.
On receiving control signals (
Read/write data is transferred between the ACRTC 10 and the frame buffer 30 through the MIVAC 20.
In the display operation, parallel data read from the frame buffer 30 is fetched into the MIVAC 20 to be converted into serial data by means of a parallel/serial converter integrated therein, thereby producing digital video signals. These digital signals are converted by the CPLT 40 into analog video signals so as to be displayed on the CRT 50. In this embodiment, although the CRT 50 is used as the output device, other output equipment, such as a printer, may also be employed.
Terminal INCLK of the operation control signals is used to receive a clock for the operation basis of the MIVAC 20. The interface signals for the ACRTC 10 include the 2CLK as the basic clock of the ACRTC 10, control signals MRD and
The INCLK as the basis of the operation of the MIVAC 20 is divided by 2, 4, 8 16, and 32 by INCLK 2006 and an INCLK divider 2009. The results are combined in a state decoder 2007 to generate a timing signal, which is used in the respective logic circuits.
The 2CLK as the basic clock of the ACRTC 10 is produced from a 2CLK generator 2008. In the 2CLK 2008, in order to effect a plurality of read and write operations in the memory cycle, the first half cycle is shorter than the second half cycle, i.e., this signal has an asymmetric shape.
For the DOTCLK, a multiplex operation is achieved on the signals attained by dividing INCLK by 1, 2, and 4 by means of a multiplexer 2010 to produce a multiplexed signal. Selection of the divided signals is automatically achieved depending on the operation mode of the MIVAC 20.
The frame buffer address MAD0 to MAD15 and MA16 to MA19 supplied from the ACRTC 10 is temporarily latched in a latch 2001 so as to be then multiplexed through a multiplexer 2003 into a row/column address, thereby generating a ten-bit address associated with the frame buffer address signals FA0 to FA9. In addition, there is integrated a column address counter 2002 such that the value of this counter and the latched address are multiplexed by the multiplexer 2003, so that the resultant signal is adopted as a portion of the column address, thereby effecting several read/write operations in a memory cycle.
The control signals from the ACRTC 10 are latched in a latch 2004. Depending on
In addition, when
When
The video signal is skewed by a skew circuit 2022 so as to be synchronized with the control signal from the ACRTC 10. For the video signal, a superimposing operation of a cursor can be achieved by use of a cursor blink 2023, or the video signals can be multiplexed through a multiplexer 2024 in response to a signal attained by dividing
By using BLINK2 of the attribute codes, a
In the case of a two chip memory configuration of
In the case of a four chip memory configuration of
In this mode, since the data buses are employed to input display data, it is impossible to effect a read operation in which 16 read operations are achieved in two memory cycles; however, when comparison is conducted in the read mode associated with four read operations per memory cycle, the operation above is applicable to a CRT which develops a higher processing speed as compared with the cases of
(1) For the display color (color/gradation), there can be specified a monochrome display represented by 1 bit/pixel, a four-color display expressed by 2 bits/pixel, and 16-color display represented by 4 bits per pixel. In the case of 1 bit/pixel, a word of the memory is loaded with information of 16 consecutive pixels in the horizontal direction. In the case of 2 bits/pixel, a word of the memory is loaded with information of 8 consecutive pixels in the horizontal direction, and in the case of 4 bits/pixel, a word of the memory is loaded with information of 4 consecutive pixels in the horizontal direction.
(2) The shift length of the shift register may be set to 4, 8, 16, or 32 bits.
(3) The access modes include a single access mode, a dual access mode in which high-speed drawing is possible, and a 2MCYC mode in which 16 display accesses are conducted in two memory cycles. In the modes 0 to 5, the single access mode is employed, whereas in the modes 6 to C, the dual access mode is used. In the modes D to F, the 2MCYC mode is adopted.
(4) The number of memories selectable is 1, 2, or 4. For the memory, there is utilized a memory such as one having a static column mode in which a plurality of read/write operations can be accomplished in a cycle.
(5) DOTCLK is generated by dividing INCLK by 1, 2, and 4. The division ratios are determined according to the respective operation modes. Based on the frequency, the screen layout of the CRT is determined for each operation mode.
(1) When CUR1 and CUR0 are both 0
The four bits of video outputs VIDEOA to VIDEOD are set to 0, and hence a black cursor is displayed.
(2) When CUR1 is 0 and CUR0 is 1
The four bits of video outputs VIDEOA to VIDEOD are set to 1 and hence a white cursor is displayed.
(3) When CUR1 is 1 and CUR0 is 0
For the four bits of video outputs VIDEOA to VIDEOD, the respective colors are reversed on the display.
(4) When CUR1 and CUR0 are both 1
For the three bits of video outputs VIDEOA to VIDEOC, the respective colors are reversed on the display, whereas VIDEOD is kept unchanged.
BLINK1=0, the cursor is not displayed, whereas for
BLINK1=1, the cursor is displayed.
As described above, according to the present invention, the data bus width of the memory can be minimized, and hence the size of the graphic processing apparatus can be reduced.
Claims
1. A graphic processing apparatus comprising:
- memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data;
- data processing means for specifying a row address in said memory means for retrieval of data from the memory locations at the different column addresses within the specified row of memory locations and processing of the retrieved data to generate graphic signals;
- memory control means;
- a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and
- a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is an integer and n>m;
- said memory control means including storage means for temporarily storing data received serially on said memory data bus from memory locations at different column addresses of the memory means row corresponding with the specified row address, and transmitting the temporarily stored data in parallel on said processor data bus to said data processing means for processing thereof to generate graphic signals.
2. A graphic processing apparatus comprising:
- memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data;
- data processing means for specifying a row address in said memory means for writing of data in the memory locations at the different column addresses within the specified row of memory locations;
- memory control means;
- a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and
- a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is an integer and n>m;
- said memory control means including multiplexer means for multiplexing data received in parallel on said processor data bus into serial data and applying the serial data to said memory data bus for writing thereof in memory locations at different column addresses of the memory means row corresponding with the specified row address.
3. A graphic processing apparatus comprising:
- memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data;
- data processing means for specifying a row address of memory locations in said memory means for transfer of a data word therewith;
- memory control means;
- a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and
- a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is a multiple of m;
- said memory control means including counter means, responsive to receipt on said processor data bus of a row address specified by said processor means to specify an n-bit data word in said memory means, for successively generating n column addresses, applying the received row address and m of the generated column addresses on said memory data bus to transfer data between said memory means and said data processor means, with the data transfer including transfer of m bits of data in parallel between said memory means and said memory control means, and transfer of n bits of data between said memory control means and said data processor means.
4. A graphic processing apparatus comprising:
- memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing pixel information;
- data processing means for specifying addresses of memory locations in said memory means for retrieval of pixel information therefrom and processing of the retrieved pixel information to generate graphic signals;
- memory control means coupled to said memory means an said data processing means for retrieving pixel information from said memory means and applying the retrieved pixel information to said data processing means for processing thereof; and
- output means connected to said memory control means for outputting processed pixel information to generate graphics.
5. A graphic processing apparatus as claimed in claim 4, wherein the pixel information comprises multi-bit pixel information units corresponding to one pixel.
6. A graphic processing apparatus as claimed in claim 4, wherein the pixel information comprises pixel information units, and wherein said memory control means includes means for selecting the number of bits in each pixel information unit.
7. A graphic processing apparatus as claimed in claim 4, wherein said memory control means includes storage means for temporarily storing pixel information retrieved from said memory means.
8. A graphic processing apparatus comprising:
- memory means, including a plurality of memory locations in an array of columns, having corresponding column addresses, and rows, having corresponding row addresses, for storing data;
- data processing means for specifying a row address in said memory means for transfer of data between the data processing means and the memory locations at the different column addresses within the specified row of memory locations;
- memory control means;
- a memory data bus having m lines and interconnecting the memory means and the memory control means to transmit m bits of data in parallel therebetween, where m is an integer; and
- a processor data bus having n lines and interconnecting the data processing means and the memory control means to transmit n bits of data in parallel therebetween, where n is an integer and n>m;
- said memory control means including storage means for temporarily storing data received on said memory bus from memory locations at different column addresses of the memory location row corresponding with the specified row address and transmitting the temporarily stored data in parallel on said processor data bus to said data processing means for processing thereof, and multiplexer means for multiplexing data received in parallel on said processor data bus into serial data and applying the serial data to said serial memory data bus for writing thereof in memory locations at different column addresses of the memory location row corresponding with the specified row address.
9. A graphic processing apparatus comprising:
- a memory which stores graphic data;
- a data processor which executes a predetermined graphic processing to generate graphic data to be stored in said memory;
- a memory controller which controls data transfer between said memory and said data processor in accordance with a request from said data processor;
- a digital to analog converter (DAC), connected to said memory controller, which outputs said graphic data read out from said memory;
- a first bus, having m (wherein m is an integer) bits width, connected between said memory and said memory controller, which transfers m bits of data in parallel; and
- a second bus, having n (wherein n is an integer, n>m) bits width, connected between said memory controller and said data processor, which transfers n bits of data in parallel;
- wherein said memory controller comprises: a storage which temporarily stores graphic data read out from said memory in successive groups of m bits of data during a predetermined period of time through said first bus, a circuit which forms n bits of data using said successive groups of m bits of data and supplies said n bits of data in parallel to said data processor through said second bus based on an indication from said data processor, and
- a converter which converts said graphic data temporarily stored in said storage into serial data which is provided to said DAC based on an indication from said data processor.
10. An apparatus according to claim 9, wherein said memory controller further comprises:
- a multiplexer which outputs the n bits graphic data transferred from said data processor to said first bus having m bits width in a time shared fashion.
11. An apparatus according to claim 9, wherein said memory controller further comprises:
- means for generating an address signal for accessing said memory plural times, in response to a signal for accessing said memory supplied from said data processor.
12. An apparatus according to claim 9, wherein graphic data to be transferred to said memory controller through said first bus is read out from said memory plural times within a unit transfer time in a time shared fashion, based on an access signal to said memory designated by said data processor.
13. An apparatus according to claim 12, wherein the graphic data transferred to said memory controller is supplied to said data processor through said second bus within a time longer than twice said unit transfer time.
14. A graphic processing apparatus comprising:
- a memory which stores graphic data;
- a data processor which executes predetermined graphic processing to generate graphic data;
- a memory controller which controls transfer of data between said memory and said data processor in response to a request from said data processor;
- a digital to analog converter (DAC), connected to said memory controller, which outputs said graphic data read out from said memory;
- a first bus having an m-bit width (wherein m is an integer) and connected between said memory and said memory controller, which transfers data of m bits in parallel; and
- a second bus having an n-bit width (wherein n is an integer and n>m) and connected between said memory controller and said data processor, which transfers data of n bits in parallel;
- wherein said memory controller concludes: a storage which temporarily stores graphic data read out from said memory successively in a predetermined period of time via said first bus, a circuit which applies said temporarily stored graphic data to said data processor as n-bit parallel data based on an indication from said data processor, and
- a converter which converts said temporarily stored graphic data into serial data and outputs the serial data to said DCA based on an indication from said data processor.
15. A graphic processing apparatus according to claim 14, wherein said memory controller includes a multiplexer which outputs n-bit graphic data transferred from said data processor on said first bus having the m-bit width successively in a time-sharing manner.
16. A graphic processing apparatus according to claim 15, wherein said memory controller includes a second circuit which generates address signals for accessing said memory plural times with respect to a signal for accessing said memory means applied from said data processor.
17. A graphic processing apparatus according to claim 15, wherein graphic data to be transferred to said memory controller via said first bus are successively read out plural times within a transfer unit time in a predetermined period of time on the basis of an access signal to said memory designated by said data processor.
18. A graphic processing apparatus according to claim 17, wherein graphic data transferred to said memory controller are applied to said data processor via said second bus within a time period more than two times said transfer unit time.
19. A graphic processing apparatus according to claim 14, wherein said memory controller includes a second circuit which generates address signals for accessing said memory plural times with respect to a signal for accessing said memory applied from said data processor.
20. A graphic processing apparatus according to claim 14, wherein graphic data to be transferred to said memory controller via said first bus are successively read out plural times within a transfer unit time in a predetermined period of time on the basis of an access signal to said memory designated by said data processor.
21. A graphic processing apparatus according to claim 20, wherein graphic data transferred to said memory controller are applied to said data processor via said second bus within a time period more than two times said transfer unit time.
22. A graphic processing apparatus comprising:
- a memory which stores graphic data, said memory being accessed by using a row address and a column address;
- a data processor which executes predetermined graphic processing to generate graphic data;
- a memory controller which controls data transfer of data between said memory and said data processor in response to a request from said data processor;
- a digital to analog converter (DAC), connected to said memory controller, which outputs said graphic data read out from said memory;
- a first bus having an m-bit width (wherein m is an integer) and connected between said memory and said memory controller, which transfers data of m bits in parallel; and
- a second bus having an n-bit width (wherein n is an integer and n>m) and connected between said memory controller and said data processor, which transfers data of n bits in parallel; and
- wherein said memory controller includes: a first circuit which reads out a plurality of graphic data at different column addresses at a same row address from said memory via said first bus successively in a predetermined period of time, a second circuit which applies said read-out graphic data to said data processor as n-bit parallel data based on an indication from said data processor, and a converter which converts said read-out graphic data into serial data and outputs the serial data to said DAC based on an indication from said data processor.
23. A graphic processing apparatus according to claim 22, wherein said memory controller includes a third circuit which successively generates a plurality of column addresses based on a signal for accessing said memory applied from said data processor.
24. A memory controller for controlling transference of data between a memory and a processor, said memory controller comprising:
- m bit terminals for coupling to said memory, wherein successive groups of m bits of data is transferred through said m bit terminals between said memory and said controller by performing plural read operations within a memory cycle (where m is an integer);
- n bit terminals for coupling to said processor, wherein n bits of data is transferred in parallel through said n bit terminals between said controller and said processor (where n is an integer and n>m);
- a storage which temporarily stores graphic data read out from said memory in successive groups of m bits of data during a predetermined period of time through said m bit terminals;
- a first circuit which forms n bits of data by combining successive groups of m bits of data from said m bit terminals and supplies said n bits of data in parallel to said n bit terminals based on an indication from said processor; and
- a converter which converts said graphic data temporarily stored in said storage into serial data which is supplied to a digital to analog converter (DAC), said DAC being connected to said memory controller.
25. A memory controller according to claim 24, wherein said successive groups of m bits of data from said m bit terminals are read out of said memory by performing plural read operations within a memory cycle based on an address specified by said processor.
26. A memory controller according to claim 25, wherein said n bits of data is applied to said processor through said n bit terminals in a unit of time more than two times said memory cycle.
27. A memory controller according to claim 24, wherein said successive groups of m bits of data each includes an m bit portion of said n bits of data.
28. A graphic processing apparatus comprising:
- a memory which stores graphic data;
- a data processor which executes a predetermined graphic processing to generate graphic data to be stored in said memory;
- a memory controller which controls data transfer between said memory and said data processor in accordance with a request from said data processor;
- a first bus, having m (wherein m is an integer) bits width, connected between said memory and said memory controller, which transfers m bits of data in parallel; and
- a second bus, having n (wherein n is an integer, n>m) bits width, connected between said memory controller and said data processor, which transfers n bits of data in parallel;
- wherein said memory controller comprises: at least one output terminal; a storage which temporarily stores graphic data read out from said memory in successive groups of m bits of data during a predetermined period of time through said first bus, a circuit which forms n bits of data using said successive groups of m bits of data and supplies said n bits of data in parallel to said data processor through said second bus based on an indication from said data processor, and a converter which converts said graphic data temporarily stored in said storage into serial data which is provided to said at least one output terminal based on an indication from said data processor.
29. An apparatus according to claim 28, wherein said memory controller further comprises:
- a multiplexer which outputs the n bits graphic data transferred from said data processor to said first bus having m bits width in a time shared fashion.
30. An apparatus according to claim 28, wherein said memory controller further comprises:
- a second circuit which generates an address signal for accessing said memory plural times, in response to a signal for accessing said memory supplied from said data processor.
31. An apparatus according to claim 28, wherein graphic data to be transferred to said memory controller through said first bus is read out from said memory plural times within a unit transfer time in a time shared fashion, based on an access signal to said memory designated by said data processor.
32. An apparatus according to claim 31, wherein the graphic data transferred to said memory controller is supplied to said data processor through said second bus within a time longer than twice said unit transfer time.
33. A graphic processing apparatus comprising:
- a memory which stores graphic data;
- a data processor which executes predetermined graphic processing to generate graphic data;
- a memory controller which controls transfer of data between said memory and said data processor in response to a request from said data processor;
- a first bus having an m-bit width (wherein m is an integer) and connected between said memory and said memory controller, which transfers data of m bits in parallel; and
- a second bus having an n-bit width (wherein n is an integer and n>m) and connected between said memory controller and said data processor, which transfers data of n bits in parallel,
- wherein said memory controller includes: at least one output terminal; a storage which temporarily stores graphic data read out from said memory successively in a predetermined period of time via said first bus, a circuit which applies said temporarily stored graphic data to said data processor as n-bit parallel data based on an indication from said data processor, and a converter which converts said temporarily stored graphic data into serial data and outputs the serial data to said at least one output terminal based on an indication from said data processor.
34. A graphic processing apparatus according to claim 33, wherein said memory controller includes a multiplexer which outputs n-bit graphic data transferred from said data processor on said first bus having the m-bit width successively in a time-sharing manner.
35. A graphic processing apparatus according to claim 34, wherein said memory controller includes a second circuit which generates address signals for accessing said memory plural times with respect to a signal for accessing said memory means applied from said data processor.
36. A graphic processing apparatus according to claim 34, wherein graphic data to be transferred to said memory controller via said first bus are successively read out plural times within a transfer unit time in a predetermined period of time on the basis of an access signal to said memory designated by said data processor.
37. A graphic processing apparatus according to claim 36, wherein graphic data transferred to said memory controller are applied to said data processor via said second bus within a time period more than two times said transfer unit time.
38. A graphic processing apparatus according to claim 33, wherein said memory controller includes a second circuit which generates address signals for accessing said memory plural times with respect to a signal for accessing said memory applied from said data processor.
39. A graphic processing apparatus according to claim 33, wherein graphic data to be transferred to said memory controller via said first bus are successively read out plural times within a transfer unit time in a predetermined period of time on the basis of an access signal to said memory designated by said data processor.
40. A graphic processing apparatus according to claim 39, wherein graphic data transferred to said memory controller are applied to said data processor via said second bus within a time period more than two times said transfer unit time.
41. A graphic processing apparatus comprising:
- a memory which stores graphic data, said memory being accessed by using a row address and a column address;
- a data processor which executes predetermined graphic processing to generate graphic data;
- a memory controller which controls transfer of data between said memory and said data processor in response to a request from said data processor;
- a first bus having an m-bit width (wherein m is an integer) and connected between said memory and said memory controller, which transfers data of m bits in parallel; and
- a second bus having an n-bit width (wherein n is an integer and n>m) and connected between said memory controller and said data processor, which transfers data of n bits in parallel; and
- wherein said memory controller includes: at least one output terminal; a first circuit which reads out a plurality of graphic data at different column addresses at a same row address from said memory via said first bus successively in a predetermined period of time, a second circuit which applies said read-out graphic data to said data processor as n-bit parallel data based on an indication from said data processor, and a converter which converts said read-out graphic data into serial data and outputs the serial data to said at least one output terminal based on an indication from said data processor.
42. A graphic processing apparatus according to claim 41, wherein said memory controller includes a third circuit which successively generates a plurality of column addresses based a signal for accessing said memory applied from said data processor.
43. A memory controller for controlling transference of data between a memory and a processor, said memory controller comprising:
- m bit terminals for coupling to said memory, wherein successive groups of m bits of data is transferred through said m bit terminals between said memory and said controller by performing plural read operations within a memory cycle (where m is an integer);
- n bit terminals for coupling to said processor, wherein n bits of data is transferred in parallel through said n bit terminals between said controller and said processor (where n is an integer and n>m);
- a storage which temporarily stores graphic data read out from said memory in successive groups of m bits of data during a predetermined period of time through said m bit terminals;
- a first circuit which forms n bits of data by combining successive groups of m bits of data from said m bit terminals and supplies said n bits of data in parallel to said n bit terminals based on an indication from said processor; and
- a converter which converts said graphic data temporarily stored in said storage into serial data which is supplied to at least one output terminal, said at least one output terminal being connected to said memory controller.
44. A memory controller according to claim 43, wherein said successive groups of m bits of data from said m bit terminals are read out of said memory by performing plural read operations within a memory cycle based on an address specified by said processor.
45. A memory controller according to claim 44, wherein said n bits of data is applied to said processor through said n bit terminals in a unit of time more than two times said memory cycle.
46. A memory controller according to claim 43, wherein said successive groups of m bits of data each includes an m bit portion of said n bits of data.
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Type: Grant
Filed: Mar 28, 2000
Date of Patent: Mar 27, 2007
Assignee: Renesas Technology Corp. (Tokyo)
Inventors: Koyo Katsura (Hitachiota), Shinichi Kojima (Takasaki), Noriyuki Kurakami (Maebashi)
Primary Examiner: Ulka J. Chauhan
Attorney: Mattingly, Stanger, Malur & Brundidge, P.C.
Application Number: 09/536,646
International Classification: G09G 5/39 (20060101);