Patents by Inventor Koyo Nitta

Koyo Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135155
    Abstract: In a data processing device, a fixed-point position control unit determines, as first control. The fixed-point position control unit causes a detection calculation unit to perform calculation processing on processing target data at a processing point in time. The saturation rate control unit instructs, as second control to be repeated by the fixed-point position control unit, the fixed-point position control unit to move at least the fixed-point position as control to increase a lower limit saturation rate proportional to a magnitude of a counted lower limit counter value with respect to a result of the first control. The fixed-point position control unit performs, as the second control, a predetermined determination on the basis of the instruction from the saturation rate control unit and the metadata, determines the fixed-point position moved for each layer, and causes calculation processing to be performed.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 25, 2024
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Saki HATTA, Hiroyuki UZAWA, Shuhei YOSHIDA, Daisuke KOBAYASHI, Yuya OMORI, Ken NAKAMURA, Koyo NITTA
  • Publication number: 20240114130
    Abstract: A video coding method is a video coding method for coding an image in units of blocks obtained by dividing an image, and in the method a computer performs processing for dividing the image into blocks, acquiring an intra-image prediction mode predicted for each block, and generating, by using a combination pattern based on the intra-image prediction mode of a plurality of blocks adjacent to at least any one block, determining whether or not the plurality of blocks are to be combined, and performing prediction for each combined block when it is determined that the plurality of blocks are to be combined.
    Type: Application
    Filed: February 16, 2021
    Publication date: April 4, 2024
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Daisuke KOBAYASHI, Ken NAKAMURA, Koyo NITTA, Yuya OMORI
  • Patent number: 11947507
    Abstract: A traffic monitoring apparatus that monitors traffic of a monitoring target network and includes a statistical information processor that acquires statistical information per specific flow of the traffic, and a packet capture unit that captures a packet of the specific flow, in which the statistical information processor includes a statistical information aggregation unit that aggregates the pieces of statistical information, and a statistical information file generation unit that generates a statistical information file based on the pieces of aggregated statistical information.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: April 2, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroyuki Uzawa, Shuhei Yoshida, Namiko Ikeda, Koyo Nitta
  • Patent number: 11916763
    Abstract: A traffic monitoring apparatus includes: a header analysis circuit configured to acquire one or more identifiers from a header of a received packet; a rule registration circuit configured to convert a rule table including rules in which one or more rule elements are registered for each of the rules into a predetermined format and register the rule table in a rule matching circuit; and the rule matching circuit configured to search for rules to be matched with the acquired identifiers.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: February 27, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yuta Ukon, Shuhei Yoshida, Shoko Oteru, Namiko Ikeda, Koyo Nitta
  • Publication number: 20240062506
    Abstract: An object detection device 10 includes an entire processing unit 110 that obtains first metadata for the entire input image by scaling the input image and performing object detection processing, a divided image narrowing unit 120 that narrows down the input image into a predetermined number of selected divided images from a group of divided images obtained by dividing the input image, a division processing unit 130 that obtains second metadata by performing object detection processing for each of the selected divided images, and a synthesis processing unit 140 that removes the second metadata obtained by the division processing unit 130 that overlaps the first metadata obtained by the entire processing unit 110, and synthesizes the first metadata not removed and the first meta data obtained by the entire processing unit 110 to output the meta data.
    Type: Application
    Filed: December 9, 2020
    Publication date: February 22, 2024
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Hiroyuki UZAWA, Saki HATTA, Shuhei YOSHIDA, Daisuke KOBAYASHI, Yuya OMORI, Ken NAKAMURA, Koyo NITTA
  • Publication number: 20240054181
    Abstract: One aspect of the present invention is an operation circuit for performing a convolution operation of input feature map information supplied as a plurality of channels and coefficient information supplied as a plurality of channels, the operation circuit including a set including at least two channels of an output feature map based on output channels and at least three sub-operation circuits, wherein at least two sub-operation circuits are allocated for each set, the sub-operation circuits included in the set execute processing of a convolution operation of the coefficient information and the input feature map information included in the set, when a specific channel of the output feature map is a zero matrix, a sub-operation circuit that performs a convolution operation of the zero matrix executes processing of a convolution operation of the coefficient information and the input feature map information to be supplied next from a channel of the output feature map and a channel of the input feature map included
    Type: Application
    Filed: December 9, 2020
    Publication date: February 15, 2024
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yuya OMORI, Ken NAKAMURA, Daisuke KOBAYASHI, Koyo NITTA
  • Publication number: 20240048466
    Abstract: An embodiment is a packet capture device including a first local timer synchronized with an external global timer, a second local timer, a time stamp assign unit for assigning a time stamp to a inputted packet signal based on the second local timer, a filter unit for selecting the packet signal to which the time stamp is assigned, a capture file generation unit for receiving the selected packet signal, and a storage unit for storing a capture file generated in the capture file generation unit, wherein the capture file generation unit calculate a difference between a timer value of the first local timer and a timer value of the second local timer to correct the time stamp value on the basis of the difference.
    Type: Application
    Filed: December 9, 2020
    Publication date: February 8, 2024
    Inventors: Hiroyuki Uzawa, Saki Hatta, Shuhei Yoshida, Koyo Nitta
  • Patent number: 11882061
    Abstract: A data sequence correction method for temporarily saving data with sequence information in a ring buffer and performing sequence correction is provided. The ring buffer includes a number of storage regions, a monitoring section having one or more continuous sequence numbers, and an acceptance section having a first or second sequence number of the monitoring section as a start sequence number and a sequence number immediately preceding the start sequence number of the monitoring section as an end sequence number. The method includes, when a value determined based on a remainder obtained by dividing a sequence number of received data by the number of storage regions is inside the acceptance section, writing the received data in a position of the storage region corresponding to the determined value, and when data are written in the entire monitoring section, reading out all the data in the monitoring section.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: January 23, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Shoko Oteru, Shuhei Yoshida, Yuta Ukon, Namiko Ikeda, Koyo Nitta
  • Publication number: 20230421463
    Abstract: A packet capture system for capturing packets flowing in a capture target network, and a plurality of stages of packet distribution devices for capturing packet of a specific flow are cascade-connected, packet distribution devices identify a capture target flow by analyzing inputted packets, packet distribution devices other than a last-stage packet distribution device are configured to distribute packets to capture packets of a flow to be captured and output packets of a flow not to be captured to a next-stage packet distribution device, and the last-stage packet distribution device is configured to filter the packets of the flow to be captured and to discard the packets of the flow not to be captured.
    Type: Application
    Filed: December 9, 2020
    Publication date: December 28, 2023
    Inventors: Saki Hatta, Hiroyuki Uzawa, Shuhei Yoshida, Koyo Nitta
  • Publication number: 20230409914
    Abstract: The integration unit 26, using configuration information of the convolutional neural network model and each filter used in each convolutional layer of the convolutional neural network model as inputs, deletes one or more pieces of activation function processing performed between the plurality of convolutional layers and integrates a plurality of filters used in the plurality of convolutional layers.
    Type: Application
    Filed: November 30, 2020
    Publication date: December 21, 2023
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Shuhei YOSHIDA, Hiroyuki UZAWA, Saki HATTA, Yuya OMORI, Daisuke KOBAYASHI, Ken NAKAMURA, Koyo NITTA
  • Patent number: 11831524
    Abstract: A state detection circuit compares a target connection with an immediate previous connection based on an identifier of an incoming packet and detects a post-transitional state of the target connection based on a control flag of the incoming packet and on a pre-transitional state of the target connection detected just before if the target connection is identical with the immediate previous connection; and a connection counting circuit increments or decrements the number of target connections only when the detected post-transitional state indicates a start or end of the target connection.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 28, 2023
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yuta Ukon, Shuhei Yoshida, Shoko Oteru, Namiko Ikeda, Koyo Nitta
  • Publication number: 20230259333
    Abstract: An embodiment is a data processor including a decimal point position control circuit configured to set a decimal point position of N-bit (N is a natural number of 2 or more) fixed-length data corresponding to each of a plurality of layers constituting a multilayered neural network, and an arithmetic processing circuit configured to perform arithmetic processing corresponding to each of the plurality of layers constituting the multilayered neural network according to a processing algorithm of the multilayered neural network on the N-bit fixed-length data for which the decimal point position has been set by the decimal point position control circuit.
    Type: Application
    Filed: July 1, 2020
    Publication date: August 17, 2023
    Inventors: Saki Hatta, Hiroyuki Uzawa, Shuhei Yoshida, Koyo Nitta
  • Patent number: 11720080
    Abstract: An optimum combination of a loop unrolling number and a circuit parallel number in a high-level synthesis is determined. A circuit synthesis information generation unit sets, as parameter candidates, a plurality of combinations of a loop unrolling number and a circuit parallel number to generate circuit synthesis information indicating a synthesis circuit obtained by high-level synthesis processing for each of the combinations. An optimum parameter determination unit calculates, for each piece of the generated circuit synthesis information, an estimation processing performance related to the synthesis circuit indicated by the circuit synthesis information, and determines an optimum combination of the loop unrolling number and the circuit parallel number based on the circuit synthesis information based on which a maximum estimation processing performance is obtained.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: August 8, 2023
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Syuhei Yoshida, Yuta Ukon, Koji Yamazaki, Koyo Nitta
  • Publication number: 20230198870
    Abstract: A packet capture apparatus includes a hardware processing unit including a filter that filters packets input from a network and an NIC and a packet storage that stores packets input from the hardware processing unit. The filter includes a packet input that receives packets input from the network, a header analysis unit that analyzes a header structure of each packet input to the packet input unit and extracts a field value of a header of the packet, a rule table in which rules including a field value of a flow to be captured are recorded, a flow identification unit that identifies a flow in which the field value extracted by the header analysis unit matches a rule in the rule table and/or does not match the rule, and a packet output that outputs a packet of the flow identified by the flow identification unit to the NIC.
    Type: Application
    Filed: May 26, 2020
    Publication date: June 22, 2023
    Inventors: Namiko Ikeda, Hiroyuki Uzawa, Koyo Nitta, Yuta Ukon, Shuhei Yoshida, Yusuke Sekihara, Shoko Oteru
  • Patent number: 11683255
    Abstract: An embodiment packet capture device comprises: a packet receiver configured to receive a packet from a network; a packet retainer configured to store the received packet in a memory to temporarily retain the received packet; a failure detector configured to determine a communication failure is present in the network; a capture controller configured to determine an operation stop address such that retention of packets from the network in time periods before and after a detection time point of the communication failure is ensured when the communication failure is detected by the failure detector; and a capture data generator configured to output the packet stored in the memory as capture data when a storage destination address of the packet stored in the memory has reached the operation stop address or when at least a predetermined waiting time period has elapsed from the detection time point of the communication failure.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 20, 2023
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Shuhei Yoshida, Yuta Ukon, Shoko Oteru, Namiko Ikeda, Koyo Nitta
  • Publication number: 20230188439
    Abstract: A traffic monitoring apparatus that monitors traffic of a monitoring target network and includes a statistical information processor that acquires statistical information per specific flow of the traffic, and a packet capture unit that captures a packet of the specific flow, in which the statistical information processor includes a statistical information aggregation unit that aggregates the pieces of statistical information, and a statistical information file generation unit that generates a statistical information file based on the pieces of aggregated statistical information.
    Type: Application
    Filed: May 26, 2020
    Publication date: June 15, 2023
    Inventors: Hiroyuki Uzawa, Shuhei Yoshida, Namiko Ikeda, Koyo Nitta
  • Publication number: 20230058896
    Abstract: An image processing device includes a division circuit that divides an input image and outputs a plurality of divided images, a first processor that performs computation of an object detection model and acquires attribute information including an attribute value of an object included in each of the divided images and a first quadrangular frame surrounding the object as first metadata, a scaling circuit that output an overall image obtained by shrinking the input image, a second processor that performs computation of the object detection model and acquires attribute information including an attribute value of an object included in the overall image and a second quadrangular frame as second metadata, and a third processor that generates third metadata of the input image by combining pieces of the attribute information of the second metadata and pieces of attribute information that are not held in common by the first and second metadata.
    Type: Application
    Filed: February 14, 2020
    Publication date: February 23, 2023
    Inventors: Hiroyuki Uzawa, Shuhei Yoshida, Koyo Nitta
  • Publication number: 20230009530
    Abstract: An embodiment is a data sequence correction method. The data sequence correction method including temporarily saving data with sequence information imparted thereto in a ring buffer, the ring buffer having a predetermined number of storage regions corresponding to the sequence information, and being provided with a monitoring section made up of one, or two or more consecutive sequence numbers, and an acceptance section in which a start or a second sequence number of the monitoring section is a start sequence number, and the sequence number ahead by a count of storage regions of the ring buffer including the start of the monitoring section is an end sequence number.
    Type: Application
    Filed: December 11, 2019
    Publication date: January 12, 2023
    Inventors: Shoko Oteru, Shuhei Yoshida, Yuta Ukon, Namiko Ikeda, Koyo Nitta
  • Publication number: 20220417118
    Abstract: A traffic monitoring apparatus includes: a header analysis circuit configured to acquire one or more identifiers from a header of a received packet; a rule registration circuit configured to convert a rule table including rules in which one or more rule elements are registered for each of the rules into a predetermined format and register the rule table in a rule matching circuit; and the rule matching circuit configured to search for rules to be matched with the acquired identifiers.
    Type: Application
    Filed: July 1, 2019
    Publication date: December 29, 2022
    Inventors: Yuta Ukon, Shuhei Yoshida, Shoko Oteru, Namiko Ikeda, Koyo Nitta
  • Publication number: 20220407788
    Abstract: A state detection circuit compares a target connection with an immediate previous connection based on an identifier of an incoming packet and detects a post-transitional state of the target connection based on a control flag of the incoming packet and on a pre-transitional state of the target connection detected just before if the target connection is identical with the immediate previous connection; and a connection counting circuit increments or decrements the number of target connections only when the detected post-transitional state indicates a start or end of the target connection.
    Type: Application
    Filed: November 5, 2019
    Publication date: December 22, 2022
    Inventors: Yuta Ukon, Shuhei Yoshida, Shoko Oteru, Namiko Ikeda, Koyo Nitta