Patents by Inventor Koyo Nitta

Koyo Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11496400
    Abstract: A network load balancing apparatus has a data buffer for each communication path of a received packet's transfer destinations, calculates a first hash value using a field value contained in the packet, determines, based on the field value of the packet or the first hash value, a communication path of a transfer destination of the packet subject to external transfer control for transmission to a predetermined external server, determines, based on the first hash value, a communication path of a transfer destination of the packet to be subject to priority control, determines, based on a second hash value based on the first hash value, a communication path of a transfer destination of the packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, and transmits the packet to a data buffer corresponding to the communication path of the transfer destination.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: November 8, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Koji Yamazaki, Saki Hatta, Shoko Oteru, Tomoaki Kawamura, Yuta Ukon, Shuhei Yoshida, Koyo Nitta
  • Publication number: 20220263733
    Abstract: A burst traffic detection device includes a packet receiver configured to receive packets from a network, a flow specification device configured to specify, in accordance with header information of the packets, flow rules, a flow information storage device configured to store flow information of the specified flow rules, a statistical information storage device configured to store statistical information including the total number of packets for each flow rule and/or the total number of bytes for each flow rule, a burst detection device configured to detect the occurrence of burst traffic in accordance with the statistical information, and a detection count storage device configured to store the number of times of the occurrence of burst traffic.
    Type: Application
    Filed: July 23, 2019
    Publication date: August 18, 2022
    Applicants: Nippon Telegraph and Telephone Corporation, Nippon Telegraph and Telephone Corporation
    Inventors: Shuhei Yoshida, Yuta Ukon, Shoko Oteru, Namiko Ikeda, Koyo Nitta
  • Publication number: 20220247697
    Abstract: A data sequence correction method for temporarily saving data with sequence information in a ring buffer and performing sequence correction is provided. The ring buffer includes a number of storage regions, a monitoring section having one or more continuous sequence numbers, and an acceptance section having a first or second sequence number of the monitoring section as a start sequence number and a sequence number immediately preceding the start sequence number of the monitoring section as an end sequence number. The method includes, when a value determined based on a remainder obtained by dividing a sequence number of received data by the number of storage regions is inside the acceptance section, writing the received data in a position of the storage region corresponding to the determined value, and when data are written in the entire monitoring section, reading out all the data in the monitoring section.
    Type: Application
    Filed: June 24, 2019
    Publication date: August 4, 2022
    Inventors: Shoko Oteru, Shuhei Yoshida, Yuta Ukon, Namiko Ikeda, Koyo Nitta
  • Publication number: 20220217069
    Abstract: An embodiment packet capture device comprises: a packet receiver configured to receive a packet from a network; a packet retainer configured to store the received packet in a memory to temporarily retain the received packet; a failure detector configured to determine a communication failure is present in the network; a capture controller configured to determine an operation stop address such that retention of packets from the network in time periods before and after a detection time point of the communication failure is ensured when the communication failure is detected by the failure detector; and a capture data generator configured to output the packet stored in the memory as capture data when a storage destination address of the packet stored in the memory has reached the operation stop address or when at least a predetermined waiting time period has elapsed from the detection time point of the communication failure.
    Type: Application
    Filed: May 14, 2019
    Publication date: July 7, 2022
    Applicants: Nippon Telegraph and Telephone Corporation, Nippon Telegraph and Telephone Corporation
    Inventors: Shuhei Yoshida, Yuta Ukon, Shoko Oteru, Namiko Ikeda, Koyo Nitta
  • Patent number: 11374874
    Abstract: An access control unit includes packet buffers provided for each of users, a packet identification unit that stores received packets in a corresponding packet buffer, a scheduling unit that decides a packet buffer to be the object of transfer, a transfer control unit that, in a case that updating of reference data can be performed at an application processing circuit, and also the packet buffer decided by the scheduling unit is different from the current packet buffer that is the object of transfer, updates to reference data corresponding to the packet buffer decided by the scheduling unit, and a buffer selection unit that connects the packet buffers decided to be the object of transfer to the packet transfer unit when updating of reference data is completed.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: June 28, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yuta Ukon, Shuhei Yoshida, Koyo Nitta
  • Publication number: 20210409344
    Abstract: An access control unit includes packet buffers provided for each of users, a packet identification unit that stores received packets in a corresponding packet buffer, a scheduling unit that decides a packet buffer to be the object of transfer, a transfer control unit that, in a case that updating of reference data can be performed at an application processing circuit, and also the packet buffer decided by the scheduling unit is different from the current packet buffer that is the object of transfer, updates to reference data corresponding to the packet buffer decided by the scheduling unit, and a buffer selection unit that connects the packet buffers decided to be the object of transfer to the packet transfer unit when updating of reference data is completed.
    Type: Application
    Filed: October 23, 2019
    Publication date: December 30, 2021
    Inventors: Yuta Ukon, Shuhei Yoshida, Koyo Nitta
  • Patent number: 11196684
    Abstract: A flow control device includes an analysis unit identifying a flow of a received packet, a plurality of queues temporarily storing packets sorted according to each flow, an allocation information storage unit storing allocation information regarding a queue allocated for each flow, a sorting unit deciding a queue to be a storage destination of the received packet and sorts the packet based on a result identified by the analysis unit and the allocation information, a saved packet holding unit saving a packet belonging to a flow determined to have no allocation information regarding the queue to be allocated by the sorting unit, and a transmission unit transmitting the packet temporarily stored in the plurality of queues and the packet saved in the saved packet holding unit to a processing unit that processes a packet.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: December 7, 2021
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Syuhei Yoshida, Yuta Ukon, Koji Yamazaki, Koyo Nitta
  • Publication number: 20210281517
    Abstract: A network load balancing apparatus has a data buffer for each communication path of a received packet's transfer destinations, calculates a first hash value using a field value contained in the packet, determines, based on the field value of the packet or the first hash value, a communication path of a transfer destination of the packet subject to external transfer control for transmission to a predetermined external server, determines, based on the first hash value, a communication path of a transfer destination of the packet to be subject to priority control, determines, based on a second hash value based on the first hash value, a communication path of a transfer destination of the packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, and transmits the packet to a data buffer corresponding to the communication path of the transfer destination.
    Type: Application
    Filed: July 5, 2019
    Publication date: September 9, 2021
    Inventors: Koji Yamazaki, Saki Hatta, Shoko Oteru, Tomoaki Kawamura, Yuta Ukon, Shuhei Yoshida, Koyo Nitta
  • Publication number: 20210116882
    Abstract: An optimum combination of a loop unrolling number and a circuit parallel number in a high-level synthesis is determined. A circuit synthesis information generation unit sets, as parameter candidates, a plurality of combinations of a loop unrolling number and a circuit parallel number to generate circuit synthesis information indicating a synthesis circuit obtained by high-level synthesis processing for each of the combinations. An optimum parameter determination unit calculates, for each piece of the generated circuit synthesis information, an estimation processing performance related to the synthesis circuit indicated by the circuit synthesis information, and determines an optimum combination of the loop unrolling number and the circuit parallel number based on the circuit synthesis information based on which a maximum estimation processing performance is obtained.
    Type: Application
    Filed: May 21, 2019
    Publication date: April 22, 2021
    Inventors: Syuhei Yoshida, Yuta Ukon, Koji Yamazaki, Koyo Nitta
  • Publication number: 20210051117
    Abstract: A flow control device includes an analysis unit identifying a flow of a received packet, a plurality of queues temporarily storing packets sorted according to each flow, an allocation information storage unit storing allocation information regarding a queue allocated for each flow, a sorting unit deciding a queue to be a storage destination of the received packet and sorts the packet based on a result identified by the analysis unit and the allocation information, a saved packet holding unit saving a packet belonging to a flow determined to have no allocation information regarding the queue to be allocated by the sorting unit, and a transmission unit transmitting the packet temporarily stored in the plurality of queues and the packet saved in the saved packet holding unit to a processing unit that processes a packet.
    Type: Application
    Filed: February 8, 2019
    Publication date: February 18, 2021
    Inventors: Syuhei Yoshida, Yuta Ukon, Koji Yamazaki, Koyo Nitta
  • Patent number: 8428137
    Abstract: In motion search using a PE array, a technique is provided for enabling high-speed calculation while avoiding bank conflict without increasing a memory for storing pixels outside the screen. When pieces of pixel data of a plurality of lines to be read from the memory 3 (reference image memory 30) exist in a same bank, the conflict bank anticipatory read control unit 10 reads pixel data of a line in advance, and a read data holding circuit 20 holds the data until timing for inputting to a PE array unit 4. Accordingly, bank conflict can be avoided when reading pixel data from the memory 3, so that smooth pipeline processing by the PE array unit 4 can be realized.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: April 23, 2013
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Koyo Nitta, Hiroe Iwasaki, Jirou Naganuma
  • Publication number: 20100215105
    Abstract: In motion search using a PE array, a technique is provided for enabling high-speed calculation while avoiding bank conflict without increasing a memory for storing pixels outside the screen. When pieces of pixel data of a plurality of lines to be read from the memory 3 (reference image memory 30) exist in a same bank, the conflict bank anticipatory read control unit 10 reads pixel data of a line in advance, and a read data holding circuit 20 holds the data until timing for inputting to a PE array unit 4. Accordingly, bank conflict can be avoided when reading pixel data from the memory 3, so that smooth pipeline processing by the PE array unit 4 can be realized.
    Type: Application
    Filed: September 12, 2008
    Publication date: August 26, 2010
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORP.
    Inventors: Koyo Nitta, Hiroe Iwasaki, Jirou Naganuma