Patents by Inventor Kozo Katayama
Kozo Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060102967Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: ApplicationFiled: December 30, 2005Publication date: May 18, 2006Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Patent number: 7012296Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: GrantFiled: May 11, 2005Date of Patent: March 14, 2006Assignee: Renesas Technology Corp.Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Publication number: 20060050558Abstract: There is provided a technology capable of enhancing reliability in rewrite of storage information in a nonvolatile memory while checking an increase in area of a memory array thereof. With a memory array configuration, individual bit lines are connected to two memory cells sharing a source, and disposed at symmetrical positions, respectively, and two lengths of metal interconnections (the bit lines) are disposed with respect to a width in the direction of a channel width of a region occupied by one of the memory cells. In contrast, respective control gates of the memory cells corresponding to two word are rendered at an identical potential, and respective memory gates thereof are rendered at an identical potential, thereby disposing three lengths of metal interconnections (a control gate control line, memory gate control line, and common source line) with respect to a length of the regions occupied by the two memory cells in the direction of a channel length.Type: ApplicationFiled: August 3, 2005Publication date: March 9, 2006Inventor: Kozo Katayama
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Publication number: 20060044873Abstract: A semiconductor device including an SOI substrate and a MONOS type nonvolatile memory cell with a first drain composed of an n+ type diffusion region and a second drain composed of a p+ type diffusion region, wherein the first and second drains are arranged in different planar locations in a silicon layer of the SOI substrate. In the data write operation of the device, electrons are injected from the first drain, and then hot electrons created by a strong electric field between a control gate and a memory gate of the memory cell are injected into a charge storage layer. In the data erase operation of the device, holes are injected from the second drain, and then hot holes created by a strong electric field between the control gate and the memory gate are injected into the charge storage layer. The semiconductor device can reduce current consumption for erasing data.Type: ApplicationFiled: July 22, 2005Publication date: March 2, 2006Inventors: Kozo Katayama, Digh Hisamoto
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Publication number: 20050258474Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: July 22, 2002Publication date: November 24, 2005Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
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Publication number: 20050219900Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: ApplicationFiled: May 11, 2005Publication date: October 6, 2005Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Patent number: 6936888Abstract: A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.Type: GrantFiled: October 2, 2003Date of Patent: August 30, 2005Assignee: Renesas Technology Corp.Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami
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Patent number: 6894344Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: GrantFiled: September 17, 2003Date of Patent: May 17, 2005Assignee: Renesas Technology Corp.Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Patent number: 6873009Abstract: It is an object of the present invention to provides a field effect transistor with extremely low leakage current. It is another object of the invention to provide a semiconductor memory device having an excellent information holding characteristic. It is a further object of the invention to provide a method for manufacturing in a simple manner a novel field effect transistor or semiconductor memory device with extremely low leakage current. According to a typical basic configuration of the present invention, a thin insulating film is inserted in a vertically disposed Schottky junction to form source and drain electrodes and a tunnel of the insulating film in the junction is controlled by a gate electrode. The gate electrode is disposed on each of both sides of a vertical channel, permitting a field effect to be exerted effectively on the junction, whereby a junction leakage in an OFF state can be made extremely low.Type: GrantFiled: June 12, 2003Date of Patent: March 29, 2005Assignee: Hitachi, Ltd.Inventors: Dai Hisamoto, Kozo Katayama
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Publication number: 20040252561Abstract: In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an EEPROM capacity to a minimum necessary amount and reduce a chip area. Data of a minimal size required for one application program and rewritten frequently is stored in the EEPROM, and the EEPROM is configured to have a capacity of about that minimal size. Data of the same size that are respectively handled by other applications and rewritten frequently are stored in the flash memory. With respect to an application that is actually used, its data stored in the flash memory is transferred to the EEPROM and used. Data transfer between the flash memory and the EEPROM is performed if necessary. Consequently, the EEPROM capacity can be reduced and chip area reduction can be achieved.Type: ApplicationFiled: June 2, 2004Publication date: December 16, 2004Inventors: Takanori Yamazoe, Takashi Tase, Junji Shigeta, Nobutaka Nagasaki, Eiji Yamasaki, Nobuhiro Oodaira, Kozo Katayama
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Publication number: 20040241944Abstract: Disclosed herein is a nonvolatile memory device having a plurality of nonvolatile memory cells. In the nonvolatile memory cell, a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side so that each of the memory cells stores information therein. The memory gate electrode and the switch gate electrodes extend in the same direction.Type: ApplicationFiled: June 29, 2004Publication date: December 2, 2004Applicant: Renesas Technology Corp.Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami
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Publication number: 20040070026Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: ApplicationFiled: September 17, 2003Publication date: April 15, 2004Applicant: Hitachi, Ltd.Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Publication number: 20040065918Abstract: A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.Type: ApplicationFiled: October 2, 2003Publication date: April 8, 2004Applicant: Hitachi, Ltd.Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami
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Patent number: 6674122Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: GrantFiled: March 4, 2003Date of Patent: January 6, 2004Assignee: Hitachi, Ltd.Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Patent number: 6653685Abstract: A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.Type: GrantFiled: November 20, 2001Date of Patent: November 25, 2003Assignee: Hitachi, Ltd.Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami
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Patent number: 6646283Abstract: A switch device includes a source, a drain, and a gate electrode which are conductive, one or more semiconductor island layer(s) formed between the source and drain, an insulating film between the source and island layer, an insulating film between the drain and island layer, an insulating layer between island layers if a plurality of island layers are provided, and a gate capacitor formed by the gate electrode, at least one island layer, and a gate insulating film provided between the gate electrode and the island layer. The electric field applied to the gate capacitor is set to be substantially parallel with a channel current flowing via the island between the source and the drain.Type: GrantFiled: November 13, 2001Date of Patent: November 11, 2003Assignee: Hitachi, Ltd.Inventors: Hajime Akimoto, Kozo Katayama
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Publication number: 20030155607Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is formed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: ApplicationFiled: March 4, 2003Publication date: August 21, 2003Applicant: Hitachi, Ltd.Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Patent number: 6590809Abstract: When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.Type: GrantFiled: January 9, 2002Date of Patent: July 8, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takanori Yamazoe, Hiroshi Yoshigi, Yoshiaki Kamigaki, Kozo Katayama, Shinichi Minami, Takeo Kanai
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Patent number: 6531735Abstract: A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.Type: GrantFiled: September 13, 2000Date of Patent: March 11, 2003Assignee: Hitachi, Ltd.Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Masataka Kato
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Publication number: 20030017672Abstract: Disclosed herein is a nonvolatile memory device having a plurality of nonvolatile memory cells. In the nonvolatile memory cell, a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side so that each of the memory cells stores information therein. The memory gate electrode and the switch gate electrodes extend in the same direction.Type: ApplicationFiled: September 18, 2002Publication date: January 23, 2003Applicant: Hitachi, Ltd.Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami