Patents by Inventor Kozo Katayama

Kozo Katayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6504755
    Abstract: A semiconductor memory device is constituted by forming two types of insulation films on the channel of an MOS transistor on which a vertical type another MOS transistor using the control gate of the MOS transistor as a substrate is stacked. Thus, a non-volatile semiconductor memory device small in size, having high reliability, high density, excellent fatigue and a random access function can be provided.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: January 7, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kozo Katayama, Dai Hisamoto
  • Publication number: 20020131299
    Abstract: When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.
    Type: Application
    Filed: January 9, 2002
    Publication date: September 19, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Takanori Yamazoe, Hiroshi Yoshigi, Yoshiaki Kamigaki, Kozo Katayama, Shinichi Minami, Takeo Kanai
  • Publication number: 20020074594
    Abstract: Disclosed herein is a nonvolatile memory device having a plurality of nonvolatile memory cells. In the nonvolatile memory cell, a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side so that each of the memory cells stores information therein. The memory gate electrode and the switch gate electrodes extend in the same direction.
    Type: Application
    Filed: November 20, 2001
    Publication date: June 20, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Kozo Katayama, Yoshiaki Kamigaki, Shinichi Minami
  • Patent number: 5422496
    Abstract: An interband single-electron tunnel/transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: June 6, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shiroo Kamohara, Toru Toyabe, Kozo Katayama, Shuichi Yamamoto, Sigeo Ihara
  • Patent number: 5323344
    Abstract: A quantum memory device in which a memory operation is enabled even if the structure of a Josephson device is reduced in size. Each memory cell of the quantum memory device includes a superconducting quantum interference device having two Josephson junctions, a write word line for supplying a current to the superconducting quantum interference device, a write data line and a magnetic field detection line magnetically coupled with the superconducting quantum interference device, a three-terminal switching device for turning a signal of the magnetic field detection line on and off to transfer the signal to a read data line, and a read word line connected to a gate of the three-terminal switching device. The junction area of the Josephson junction is made small to oscillate a magnetic flux so that information is stored in accordance with the phase of oscillation of the magnetic flux.
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: June 21, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kozo Katayama, Shiroo Kamohara
  • Patent number: 5258625
    Abstract: An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.
    Type: Grant
    Filed: October 15, 1992
    Date of Patent: November 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Shiroo Kamohara, Toru Toyabe, Kozo Katayama, Shuichi Yamamoto, Sigeo Ihara
  • Patent number: 4856754
    Abstract: A shuttering used for forming concrete comprises a plate with a plurality of through holes opening on both its face and reverse, and a double woven fabric consisting of a face tissue which permits passage of water but prevents concrete from passing and a reverse tissue opposed to the face of the plate and relatively displaceable with respect to the face of the plate; the surplus water oozing out of placed concrete flows through gaps formed by the reverse tissue between said plate and the face tissue as well as the through holes of said plate.
    Type: Grant
    Filed: June 3, 1988
    Date of Patent: August 15, 1989
    Assignee: Kabushiki Kaisha Kumagaigumi
    Inventors: Takayoshi Yokota, Shigekazu Horiya, Sadao Uno, Kozo Katayama, Daijiro Tanabe