Patents by Inventor Kozo Kimura
Kozo Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080209192Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.Type: ApplicationFiled: April 28, 2008Publication date: August 28, 2008Inventors: Kazuya Furukawa, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazushi Kurata, Shigeki Fujii, Toshio Sugimura
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Patent number: 7395408Abstract: The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data includes two instructions, the instruction decoding unit 120 forms all the PEs into two groups, so as to assign one instruction to each group. By making it possible to execute, in parallel, not only one type of instruction but also instructions that are different from each other, it is possible to improve the utilization efficiency of the parallel execution processor 100.Type: GrantFiled: October 16, 2003Date of Patent: July 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Tanaka, Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara
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Patent number: 7386707Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.Type: GrantFiled: January 8, 2003Date of Patent: June 10, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazushi Kurata, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazuya Furukawa, Shigeki Fujii, Toshio Sugimura
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Patent number: 7315934Abstract: A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.Type: GrantFiled: February 28, 2003Date of Patent: January 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyuki Morishita, Atsushi Ito, Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara, Akira Miyoshi, Hiroshi Kadota
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Publication number: 20070286275Abstract: The present invention provides an integrated circuit for video/audio processing in which the design resources obtained by the development of video/audio devices can be used also for other types of video/audio devices. The integrated circuit comprises a microcomputer block 2 including a CPU, a stream I/O block 4 for inputting/outputting video and audio streams to and from an external device, a media processing block 3 for executing the media processing including at least one of the compression and decompression of the video and audio streams, etc. inputted to the stream I/O block 4, an AV IO block 5 for converting the video and audio streams subjected to the media processing in the media processing block 3 into video and audio signals and outputting these signals to the external device, etc, and a memory IF block 6 for controlling the data transfer between the microcomputer block 2, the stream I/C block 4, the media processing block 3 and the AV IO block 5 and an external memory 9.Type: ApplicationFiled: April 1, 2005Publication date: December 13, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kozo Kimura, Tokuzo Kiyohara, Hiroshi Mizuno, Junji Michiyama, Tomohiko Kitamura, Ryoji Yamaguchi, Manabu Kuroda, Nobuhiko Yamada, Hideyuki Ohgose, Akifumi Yamana
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Patent number: 7236948Abstract: A foot shape information distributing system for distributing foot shape information including cross section data generated based on anatomical feature points of a foot. Eleven defined cross sections (A to K) are determined and stored. Server machine distributes foot shape information including the same cross section data and the same feature points as user terminal stores. Based upon the cross sections, shoes are selected or manufactured for a customer.Type: GrantFiled: November 15, 2000Date of Patent: June 26, 2007Assignees: National Institute of Advanced Industrial Science and Technology, I-Ware Laboratory Co., Ltd.Inventors: Masaaki Mochimaru, Makiko Kouchi, Kozo Kimura, Tsuneaki Utsumi
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Patent number: 7079583Abstract: A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing.Type: GrantFiled: October 24, 2001Date of Patent: July 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura
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Patent number: 7020787Abstract: A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.Type: GrantFiled: December 18, 2002Date of Patent: March 28, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara
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Patent number: 6901454Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.Type: GrantFiled: November 7, 2002Date of Patent: May 31, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nobuo Higaki, Tetsuya Tanaka, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida
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Publication number: 20050102440Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.Type: ApplicationFiled: December 8, 2004Publication date: May 12, 2005Inventors: Nobuo Higaki, Tetsuya Tanaka, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura
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Patent number: 6829302Abstract: A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.Type: GrantFiled: December 20, 2001Date of Patent: December 7, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyuki Morishita, Kosuke Yoshioka, Hideshi Nishida, Makoto Hirai, Ryuji Matsuura, Toshiaki Tsuji, Kozo Kimura, Tokuzo Kiyohara
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Patent number: 6809777Abstract: A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.Type: GrantFiled: December 18, 2001Date of Patent: October 26, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroyuki Oka, Hideshi Nishida, Kosuke Yoshioka, Tokuzo Kiyohara, Makoto Hirai, Kozo Kimura, Ryuji Matsuura, Hiroyuki Morishita, Toshiaki Tsuji
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Publication number: 20040133765Abstract: The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data includes two instructions, the instruction decoding unit 120 forms all the PEs into two groups, so as to assign one instruction to each group. By making it possible to execute, in parallel, not only one type of instruction but also instructions that are different from each other, it is possible to improve the utilization efficiency of the parallel execution processor 100.Type: ApplicationFiled: October 16, 2003Publication date: July 8, 2004Inventors: Takeshi Tanaka, Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara
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Publication number: 20040010321Abstract: A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.Type: ApplicationFiled: February 28, 2003Publication date: January 15, 2004Inventors: Hiroyuki Morishita, Atsushi Ito, Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara, Akira Miyoshi, Hiroshi Kadota
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Publication number: 20030149864Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.Type: ApplicationFiled: January 8, 2003Publication date: August 7, 2003Inventors: Kazuya Furukawa, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Kazushi Kurata, Shigeki Fujii, Toshio Sugimura
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Publication number: 20030135779Abstract: A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.Type: ApplicationFiled: December 18, 2002Publication date: July 17, 2003Inventors: Satoshi Takashima, Hideshi Nishida, Kozo Kimura, Tokuzo Kiyohara
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Publication number: 20030110329Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.Type: ApplicationFiled: November 7, 2002Publication date: June 12, 2003Inventors: Nobuo Higaki, Tetsuya Tanaka, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida
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Publication number: 20030007565Abstract: A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by means of the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.Type: ApplicationFiled: December 20, 2001Publication date: January 9, 2003Inventors: Hiroyuki Morishita, Kosuke Yoshioka, Hideshi Nishida, Makoto Hirai, Ryuji Matsuura, Toshiaki Tsuji, Kozo Kimura, Tokuzo Kiyohara
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Publication number: 20020106136Abstract: A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.Type: ApplicationFiled: December 18, 2001Publication date: August 8, 2002Inventors: Hiroyuki Oka, Hideshi Nishida, Kosuke Yoshioka, Tokuzo Kiyohara, Makoto Hirai, Kozo Kimura, Ryuji Matsuura, Hiroyuki Morishita, Toshiaki Tsuji
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Publication number: 20020041626Abstract: A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing.Type: ApplicationFiled: October 24, 2001Publication date: April 11, 2002Inventors: Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura