Patents by Inventor Kozo Watanabe

Kozo Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100136412
    Abstract: A method for producing a lithium-containing composite oxide represented by General Formula (1): LixMyMe1?yO2+???(1) where M represents at least one element selected from the group consisting of Ni, Co and Mn, Me represents a metal element that is different from M, 0.95?x?1.10 and 0.1?y?1. A lithium compound and a compound that contains M and Me are baked. The thus-obtained baked product is washed with a washing solution that contains one or more water-soluble polar aprotic solvents such as N-methyl-2-pyrrolidone (NMP), N,N?-dimethylimidazolidinone (DMI) and dimethylsulfoxide (DMSO).
    Type: Application
    Filed: November 17, 2009
    Publication date: June 3, 2010
    Inventor: Kozo WATANABE
  • Patent number: 7687914
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 30, 2010
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Publication number: 20100068627
    Abstract: A nonaqueous electrolyte secondary battery includes: a positive electrode 4 including a positive electrode current collector and a positive electrode mixture layer containing a positive electrode active material and a binder, the positive electrode mixture layer being provided on the positive electrode current collector; a negative electrode 5; a porous insulating layer 6 interposed between the positive electrode 4 and the negative electrode 5; and a nonaqueous electrolyte. The positive electrode 4 has a tensile extension percentage of equal to or higher than 3.0%. The positive electrode current collector is made of aluminium containing iron. In this manner, the tensile extension percentage of the positive electrode is increased without a decrease in capacity of the nonaqueous electrolyte secondary battery. Accordingly, even when the nonaqueous electrolyte secondary battery is destroyed by crush, occurrence of short-circuit in the nonaqueous electrolyte secondary battery can be suppressed.
    Type: Application
    Filed: August 5, 2008
    Publication date: March 18, 2010
    Inventors: Yoshiyuki Muraoka, Kozo Watanabe, Kaoru Inoue, Yukihiro Okada
  • Publication number: 20100040940
    Abstract: An electrode in sheet form includes a current collector and an electrode mixture layer carried on each side thereof. The electrode is bent in the longitudinal direction thereof, to cause a large number of cracks in at least the electrode mixture layer to be positioned on the inner side of the current collector when wound, such that the cracks extend from the surface of the electrode mixture layer to the current collector in the direction intersecting with the longitudinal direction of the electrode. This bending process includes the steps of: bending the electrode at a curvature that is smaller than that of the winding core at least once; and thereafter bending the electrode at a curvature that is equal to or larger than that of the winding core. For example, this process is performed by arranging rollers such that their diameters decrease gradually and pressing the electrode against these rollers. This invention provides an electrode that does not break when wound to form an electrode assembly.
    Type: Application
    Filed: October 19, 2009
    Publication date: February 18, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Kozo WATANABE, Masao Fukunaga, Ichiro Yasuoka, Toshiro Kume
  • Patent number: 7663179
    Abstract: A semiconductor device having a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, the transistors each including a gate insulating film formed over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the corresponding gate electrode. Sidewall spacers of the first field effect transistor are different from those of at least the second field effect transistors. Also, the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor and the gate electrode of the third field effect transistor has a length different from that of either the first field effect transistor or second field effect transistor.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: February 16, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Masaaki Shinohara, Kozo Watanabe, Fukuo Owada, Takashi Aoyama
  • Patent number: 7622218
    Abstract: An electrode in sheet form includes a current collector and an electrode mixture layer carried on each side thereof. The electrode is bent in the longitudinal direction thereof, to cause a large number of cracks in at least the electrode mixture layer to be positioned on the inner side of the current collector when wound, such that the cracks extend from the surface of the electrode mixture layer to the current collector in the direction intersecting with the longitudinal direction of the electrode. This bending process includes the steps of: bending the electrode at a curvature that is smaller than that of the winding core at least once; and thereafter bending the electrode at a curvature that is equal to or larger than that of the winding core. For example, this process is performed by arranging rollers such that their diameters decrease gradually and pressing the electrode against these rollers. This invention provides an electrode that does not break when wound to form an electrode assembly.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: November 24, 2009
    Assignee: Panasonic Corporation
    Inventors: Kozo Watanabe, Masao Fukunaga, Ichiro Yasuoka, Toshiro Kume
  • Publication number: 20090243027
    Abstract: To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.
    Type: Application
    Filed: March 8, 2009
    Publication date: October 1, 2009
    Inventors: Kunihiko KATO, Shigeya TOYOKAWA, Kozo WATANABE, Masatoshi TAYA
  • Patent number: 7589423
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: September 15, 2009
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 7553587
    Abstract: A non-aqueous electrolyte secondary battery has an insulating porous membrane, on at least one of a positive electrode, negative electrode, and separator thereof. The membrane contains an inorganic filler, and an active agent for dispersing the inorganic filler uniformly.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: June 30, 2009
    Assignee: Panasonic Corporation
    Inventor: Kozo Watanabe
  • Publication number: 20090152644
    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.
    Type: Application
    Filed: January 6, 2009
    Publication date: June 18, 2009
    Inventors: Kozo WATANABE, Shoji YOSHIDA, Masashi SAHARA, Shinichi TANABE, Takashi HASHIMOTO
  • Patent number: 7504297
    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: March 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kozo Watanabe, Shoji Yoshida, Masashi Sahara, Shinichi Tanabe, Takashi Hashimoto
  • Publication number: 20080285193
    Abstract: A power supply apparatus includes: a plurality of batteries; a changeover portion switching the connection between the plurality of batteries; a short-circuit battery detection portion, if an internal short-circuit is produced in any of the plurality of batteries, detecting this internal short-circuit battery; and a changeover control portion, if the short-circuit battery detection portion detects the internal short-circuit battery, allowing the changeover portion to switch the connection between the plurality of batteries in such a way that this internal short-circuit battery and at least one of the other batteries are connected in series to thereby form a closed circuit.
    Type: Application
    Filed: May 12, 2008
    Publication date: November 20, 2008
    Inventors: Kozo WATANABE, Hajime NISHINO, Kazuya MAEGAWA
  • Publication number: 20080233477
    Abstract: According to a positive electrode for a lithium ion secondary battery comprising a current collector and a mixture layer containing a transition metal-containing complex oxide as a positive electrode active material formed on the current collector, wherein the mixture layer has surface roughness of 0.1 ?m or more and 0.5 ?m or less in terms of a Ra value and the mixture layer has a surface treated layer treated with a coupling agent on the surface, it is possible to obtain a positive electrode which is excellent in suppression of moisture absorption. By using the positive electrode, it is possible to obtain a lithium ion secondary battery which is excellent in storage characteristics and causes less battery swelling since the amount of a gas generated upon charging and discharging decreases.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 25, 2008
    Inventors: Keiichi TAKAHASHI, Kozo WATANABE, Kensuke NAKURA
  • Publication number: 20080211056
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: October 30, 2007
    Publication date: September 4, 2008
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohlko Yamamoto
  • Patent number: 7411302
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: August 12, 2008
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 7397104
    Abstract: A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: July 8, 2008
    Assignee: Elpida Memory, Inc.
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Patent number: 7348245
    Abstract: Manufacturing method of a semiconductor device for forming a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, including forming a gate insulating film over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the gate electrode associated with each of the first through third field effect transistors. The sidewall spacers of at least the first field effect transistor have a different width than that of at least the second field effect transistor, the gate electrode of the third field effect transistor has a different length than that of at least the first field effect transistor for memory and the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: March 25, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masaaki Shinohara, Kozo Watanabe, Fukuo Owada, Takashi Aoyama
  • Publication number: 20070246780
    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.
    Type: Application
    Filed: March 19, 2007
    Publication date: October 25, 2007
    Inventors: Kozo Watanabe, Shoji Yoshida, Masashi Sahara, Shinichi Tanabe, Takashi Hashimoto
  • Publication number: 20070231700
    Abstract: A non-aqueous electrolyte secondary battery has an insulating porous membrane, on at least one of a positive electrode, negative electrode, and separator thereof. The membrane contains an inorganic filler, and an active agent for dispersing the inorganic filler uniformly.
    Type: Application
    Filed: December 28, 2006
    Publication date: October 4, 2007
    Inventor: Kozo Watanabe
  • Publication number: 20070222080
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: May 24, 2007
    Publication date: September 27, 2007
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto