Patents by Inventor Krishna C. Saraswat
Krishna C. Saraswat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11588066Abstract: Tandem solar cell configurations are provided where at least one of the cells is a metal chalcogenide cell. A four-terminal tandem solar cell configuration has two electrically independent solar cells stacked on each other. A two-terminal solar cell configuration has two electrically coupled solar cells (same current through both cells) stacked on each other. Carrier selective contacts can be used to make contact to the metal chalcogenide cell (s) to alleviate the troublesome Fermi level pinning issue. Carrier-selective contacts can also remove the need to provide doping of the metal chalcogenide. Doping of the metal chalcogenide can be provided by charge transfer. These two ideas can be practiced independently or together in any combination.Type: GrantFiled: November 5, 2019Date of Patent: February 21, 2023Assignee: The Board of Trustees of the Leland Stanford Junior UnivesityInventors: Koosha Nassiri Nazif, Raisul Islam, Jin-Hong Park, Krishna C. Saraswat
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Publication number: 20210359150Abstract: Tandem solar cell configurations are provided where at least one of the cells is a metal chalcogenide cell. A four-terminal tandem solar cell configuration has two electrically independent solar cells stacked on each other. A two-terminal solar cell configuration has two electrically coupled solar cells (same current through both cells) stacked on each other. Carrier selective contacts can be used to make contact to the metal chalcogenide cell (s) to alleviate the troublesome Fermi level pinning issue. Carrier-selective contacts can also remove the need to provide doping of the metal chalcogenide. Doping of the metal chalcogenide can be provided by charge transfer. These two ideas can be practiced independently or together in any combination.Type: ApplicationFiled: November 5, 2019Publication date: November 18, 2021Inventors: Koosha Nassiri Nazif, Raisul Islam, Jin-Hong Park, Krishna C. Saraswat
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Patent number: 9595812Abstract: A crossed nanobeam structure for strain engineering in semiconductor devices is provided. For example, such a structure can be used for a low-threshold germanium laser. While the photonic crystal nanobeam enables light confinement in a subwavelength volume with small optical loss, another crossing nanobeam induces high tensile strain in the small region where the optical mode is tightly confined. As maintaining a small optical loss and a high tensile strain reduces the required pumping for achieving net optical gain beyond cavity losses, this technique can be used to develop an extremely low-threshold Ge laser source. Moreover, the structure can be easily integrated into electronic and photonic circuits.Type: GrantFiled: June 23, 2015Date of Patent: March 14, 2017Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Donguk Nam, Jan A. Petykiewicz, Devanand S. Sukhdeo, Shashank Gupta, Jelena Vuckovic, Krishna C. Saraswat
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Patent number: 9343608Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.Type: GrantFiled: August 15, 2014Date of Patent: May 17, 2016Assignee: Board of Regents, The University of Texas SystemInventors: Yeul Na, Krishna C Saraswat
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Publication number: 20150372455Abstract: A crossed nanobeam structure for strain engineering in semiconductor devices is provided. For example, such a structure can be used for a low-threshold germanium laser. While the photonic crystal nanobeam enables light confinement in a subwavelength volume with small optical loss, another crossing nanobeam induces high tensile strain in the small region where the optical mode is tightly confined. As maintaining a small optical loss and a high tensile strain reduces the required pumping for achieving net optical gain beyond cavity losses, this technique can be used to develop an extremely low-threshold Ge laser source. Moreover, the structure can be easily integrated into electronic and photonic circuits.Type: ApplicationFiled: June 23, 2015Publication date: December 24, 2015Inventors: Donguk Nam, Jan A. Petykiewicz, Devanand S. Sukhdeo, Shashank Gupta, Jelena Vuckovic, Krishna C. Saraswat
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Publication number: 20150136214Abstract: Junction-less solar cells having three or more terminals are provided. Electron- and hole-selective contacts and interfaces are used in combination with two or more absorber layers having different bandgaps to provide multi-material solar cells that have no requirement for either lattice matching or current matching.Type: ApplicationFiled: November 20, 2014Publication date: May 21, 2015Inventors: Raisul Islam, Gautam Shine, Aneesh Nainani, Krishna C. Saraswat
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Publication number: 20140363917Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.Type: ApplicationFiled: August 15, 2014Publication date: December 11, 2014Applicant: The Board of Trustees of the Leland Stanford Junior UniversityInventors: YEUL NA, KRISHNA C. SARASWAT
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Patent number: 8896083Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.Type: GrantFiled: March 15, 2013Date of Patent: November 25, 2014Assignee: Board of Regents, The University of Texas SystemInventors: Yeul Na, Krishna C. Saraswat
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Publication number: 20140308801Abstract: Bonding of one or more semiconductor layers to a glass substrate is facilitated by depositing spin-on-glass (SOG) on the top of the semiconductor layers. The SOG is then bonded to the glass substrate, and after that, the original substrate of the semiconductor layers is removed. The resulting structure has the semiconductor layers disposed on the glass substrate with a layer of SOG sandwiched between. Bonding is always between glass and glass, and is independent of the composition of the target layers. Thus, it can provide “anything on glass”. For example, X-on-insulator (XOI), where X can be silicon, germanium, GaAs, GaN, SiC, graphene, etc. The spin-on-glass also helps with the surface roughness requirement.Type: ApplicationFiled: April 11, 2014Publication date: October 16, 2014Applicant: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Jae Hyung Lee, Woo Shik Jung, Krishna C. Saraswat
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Publication number: 20140264501Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: SEMICONDUCTOR RESEARCH CORPORATIONInventors: Yeul Na, KRISHNA C. SARASWAT
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Patent number: 7919381Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.Type: GrantFiled: March 8, 2010Date of Patent: April 5, 2011Assignees: Canon Kabushiki Kaisha, The Board of Trustees of the Leland Stanford Junior UniversityInventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
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Patent number: 7772078Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.Type: GrantFiled: August 26, 2008Date of Patent: August 10, 2010Assignees: The Board of Trustees of the Leland Stanford Junior University, Canon Kabushiki KaishaInventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
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Publication number: 20100159678Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.Type: ApplicationFiled: March 8, 2010Publication date: June 24, 2010Applicants: CANON KABUSHIKI KAISHA, The Board of Trustees of the Leland Stanford Junior UniversityInventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
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Publication number: 20090061604Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.Type: ApplicationFiled: August 26, 2008Publication date: March 5, 2009Applicants: CANON KABUSHIKI KAISHA, The Board of Trustees of the Leland Stanford Junior UniversityInventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
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Patent number: 7495313Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.Type: GrantFiled: July 22, 2005Date of Patent: February 24, 2009Assignees: Board of Trustees of the Leland Stanford Junior University, Canon Kabushiki KaishaInventors: Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
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Patent number: 7271458Abstract: Excellent capacitor-voltage characteristics with near-ideal hysteresis are realized in a capacitive-like structure that uses an electrode substrate-type material with a high-k dielectric layer having a thickness of a few-to-several Angstroms capacitance-based SiO2 equivalent (“TOx, Eq”). According to one particular example embodiment, a semiconductor device structure has an electrode substrate-type material having a Germanium-rich surface material. The electrode substrate-type material is processed to provide this particular electrode surface material in a form that is thermodynamically stable with a high-k dielectric material. A dielectric layer is then formed over the electrode surface material with the high-k dielectric material at a surface that faces, lies against and is thermodynamically stable with the electrode surface material.Type: GrantFiled: March 31, 2003Date of Patent: September 18, 2007Assignee: The Board of Trustees of the LeLand Stanford Junior UniversityInventors: Chi On Chui, Krishna C. Saraswat, Baylor B. Triplett, Paul McIntyre
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Patent number: 5469742Abstract: An acoustic temperature and/or film thickness monitoring system for semiconductor wafers in which the velocity of acoustic waves in the wafer is employed to measure temperature and/or thickness.Type: GrantFiled: March 9, 1993Date of Patent: November 28, 1995Inventors: Yong J. Lee, Butrus T. Khuri-Yakub, Krishna C. Saraswat
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Patent number: 5250818Abstract: MOS transistors are formed in thin films of Ge/Si alloys (Ge.sub.x Si.sub.1-x). According to the process of the present invention, polycrystalline films of Ge/Si are deposited using commercially-available LPCVD equipment, which in the preferred process uses silane and germane as the sources of Ge and Si. The deposited Ge.sub.x Si.sub.1-x films are polycrystalline at temperatures for processing down to as below 400.degree. C., and the films can be doped heavily by ion implantation and annealing at temperatures as low as 600.degree. C. to give high mobility and dopant activation yielding very low resistivity. By carrying out the annealing step in the formation of the thin film transistors in the temperature range of 400.degree. to 500.degree. C., the films provide very large grain size, minimizing the impact of grain boundaries in the polycrystalline films where the thin film transistors are to be formed. As a result, thin film MOS transistors are fabricated at temperatures below 500.degree. C.Type: GrantFiled: March 1, 1991Date of Patent: October 5, 1993Assignee: Board of Trustees of Leland Stanford UniversityInventors: Krishna C. Saraswat, Tsu-Jae King
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Patent number: 4913929Abstract: A novel cold wall single wafer rapid thermal/microwave remote plasma multiprocessing reactor comprising a vacuum chamber having means for mounting a wafer in the chamber, means for providing optical flux mounted adjacent one wall facing the back side of the wafer for optical heating of the wafer, and ports for plasma injection such that remote plasma can be generated and pumped into the chamber. Ports are provided for gas injection both through the plasma generating chamber and for non-plasma injection. The plasma and non-plasma ports are connected through separate manifolds to a plurality of gas sources. The comprehensive reactor design is such that several wafer processing steps can be done sequentially in situ, while providing for optimization of each processing step.Type: GrantFiled: April 21, 1987Date of Patent: April 3, 1990Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Mehrdad M. Moslehi, Krishna C. Saraswat
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Patent number: RE37032Abstract: Layered structures (e.g., Al-Si/Ti/Al-Si . . . ) and homogeneous alloys of aluminum and aluminum/1 at. % silicon with titanium and tungsten and other refractory metals have been found to significantly reduce hillock densities in the films when small amounts of titanium or tungsten are homogeneously added. However, the resistivity of the films can become excessive. In addition, a new type of low density hillock can form. Layering of the films eliminates all hillocks and results in films of low resistivity. Such layered and homogeneous films made with Al-Si and Ti were found to be dry etchable. Electrical shorts in test structures with two levels of metal and LPCVD SiO2 as an interlayer dielectric have been characterized and layered films using Al-Si and Ti gave excellent results.Type: GrantFiled: February 19, 1999Date of Patent: January 30, 2001Assignee: The Board of Trustees of the Leland Stanford Jr. UniversityInventors: Donald S. Gardner, Krishna C. Saraswat, Troy W. Barbee, Jr.