Abstract: A process sequence for forming a multilevel tungsten interconnect array begins from a device level already planarized; alternate layers of silicon nitride and oxide are deposited. Via holes are then defined by masking, and anisotropically etched entirely through the nitride and oxide layers down to the device level (by reactive ion etching). Then the trenches for metal lines are defined intermediate the via holes and selectively plasma etched through the topmost layer of nitride and the topmost layer of dielectric, stopping atop the second layer of nitride. The oxide sidewalls of the metal line trenches and via holes are then etched laterally, using a wet etching process that results in much slower etching of the nitride layer so that nitride overhangs are formed that will protect the oxide sidewalls during subsequent vertical etchings.

Abstract: Layered structures (e.g., Al-Si/Ti/Al-Si . . . ) and homogeneous alloys of aluminum and aluminum/1 at. % silicon with titanium and tungsten and other refractory metals have been found to significantly reduce hillock densities in the films when small amounts of titanium or tungsten are homogeneously added. However, the resistivity of the films can become excessive. In addition, a new type of low density hillock can form. Layering of the films eliminates all hillocks and results in films of low resistivity. Such layered and homogeneous films made with Al-Si and Ti were found to be dry etchable. Electrical shorts in test structures with two levels of metal and LPCVD SiO.sub.2 as an interlayer dielectric have been characterized and layered films using Al-Si and Ti gave excellent results.