Patents by Inventor Krishna R. Tunga

Krishna R. Tunga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190148260
    Abstract: An electrical package may comprise a first substrate with a first substrate surface, and a microprocessor chip connected to the first substrate surface. The microprocessor chip may comprise a first chip surface that electrically connects to the first substrate surface, and a second chip surface located opposite the first chip surface. The electrical package may comprise a heat spreader assembly that comprises a lid section and a contact surface thermally connected to the second-chip surface. The electrical package may also comprise a pedestal between the contact surface and the lid section. The pedestal may comprise a first end that is located near the contact surface and a second end that is located near the lid section. The second end may be wider than the first end.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Inventors: Kamal K. Sikka, Hilton T. Toy, Krishna R. Tunga, Thomas Weiss
  • Patent number: 10276534
    Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 10276535
    Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Publication number: 20190122574
    Abstract: A computer-implemented method, a computer program product, and an incremental learning system are provided for language learning and speech enhancement. The method includes transforming acoustic utterances uttered by an individual into textual representations thereof, by a voice-to-language processor configured to perform speech recognition. The method further includes accelerating speech development in the individual, by an incremental learning system that includes the voice-to-language processor and that processes the acoustic utterances using natural language processing and analytics to determine and incrementally provide new material to the individual for learning.
    Type: Application
    Filed: October 25, 2017
    Publication date: April 25, 2019
    Inventors: Mahmoud Amin, Zhenxing Bi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Krishna R. Tunga, Loma Vaishnav
  • Patent number: 10249548
    Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
  • Publication number: 20180368757
    Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.
    Type: Application
    Filed: November 2, 2017
    Publication date: December 27, 2018
    Inventors: Mahmoud AMIN, Zhenxing BI, Lawrence A. CLEVENGER, Leigh Anne H. CLEVENGER, Krishna R. TUNGA
  • Publication number: 20180368756
    Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 27, 2018
    Inventors: MAHMOUD AMIN, ZHENXING BI, LAWRENCE A. CLEVENGER, LEIGH ANNE H. CLEVENGER, KRISHNA R. TUNGA
  • Patent number: 10108753
    Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Publication number: 20180301355
    Abstract: A method to control warpage in a semiconductor chip package that includes: attaching a semiconductor chip to a semiconductor chip package; attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (CTE) less than that of the substrate on which the chip is assembled; attaching the semiconductor chip package to a laminate substrate; and removing the stiffener.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 18, 2018
    Inventors: Tuhin Sinha, Krishna R. Tunga
  • Publication number: 20180108626
    Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
    Type: Application
    Filed: July 6, 2017
    Publication date: April 19, 2018
    Inventors: Ekta Misra, Krishna R. Tunga
  • Patent number: 9947598
    Abstract: A methodology and associated wafer level assembly of testing crackstop structure designs. The wafer level semiconductor assembly includes: a substrate structure shaped to define a set of horizontal directions; a metallization layer located on top of the substrate structure, with the metallization layer including a crackstop structure formed therein in accordance with a crackstop structure design; and a tensioned layer located on top of the metallization layer, with the tensioned layer being made of material having internal tensile forces oriented in the horizontal directions. The tensile forces promote horizontal direction crack propagation in the metallization layer so that the crackstop structure design can be tested more rigorously and reliably before deciding on the crackstop design structure to put into mass production (which mass produced product would typically not include the tensioned layer).
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Krishna R. Tunga, Karen P. McLaughlin, Charles L. Arvin, Brian R. Sundlof, Steven P. Ostrander, Christopher D. Muzzy, Thomas A. Wassick
  • Publication number: 20180082922
    Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.
    Type: Application
    Filed: October 23, 2017
    Publication date: March 22, 2018
    Inventors: Kamal K. Sikka, Krishna R. Tunga
  • Publication number: 20180082919
    Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.
    Type: Application
    Filed: August 8, 2017
    Publication date: March 22, 2018
    Inventors: Kamal K. Sikka, Krishna R. Tunga
  • Publication number: 20180076101
    Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 15, 2018
    Inventors: Sushumna Iruvanti, Shidong Li, Marek A. Orlowski, David L. Questad, Tuhin Sinha, Krishna R. Tunga, Thomas A. Wassick, Randall J. Werner, Jeffrey A. Zitz
  • Publication number: 20180061800
    Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Application
    Filed: October 26, 2017
    Publication date: March 1, 2018
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Publication number: 20180061799
    Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Application
    Filed: August 8, 2017
    Publication date: March 1, 2018
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 9865557
    Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Publication number: 20170351783
    Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 9837333
    Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kamal K. Sikka, Krishna R. Tunga
  • Patent number: 9754905
    Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekta Misra, Krishna R. Tunga