Patents by Inventor Krishna R. Tunga
Krishna R. Tunga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200303339Abstract: Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.Type: ApplicationFiled: March 19, 2019Publication date: September 24, 2020Inventors: CHARLES L. ARVIN, Clement J. Fortin, Christopher D. Muzzy, Krishna R. Tunga, Thomas Weiss
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Patent number: 10777482Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.Type: GrantFiled: May 7, 2019Date of Patent: September 15, 2020Assignee: ELPIS TECHNOLOGIES INC.Inventors: Charles L. Arvin, Steven P. Ostrander, Krishna R. Tunga
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Patent number: 10770385Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.Type: GrantFiled: July 26, 2018Date of Patent: September 8, 2020Assignee: International Business Machines CorporationInventors: Anson J. Call, Brian W. Quinlan, Krishna R. Tunga
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Patent number: 10756031Abstract: An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.Type: GrantFiled: May 10, 2019Date of Patent: August 25, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Franklin M. Baez, Brian W. Quinlan, Charles L. Reynolds, Krishna R. Tunga, Thomas Weiss
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Patent number: 10665524Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.Type: GrantFiled: August 8, 2017Date of Patent: May 26, 2020Assignee: International Business Machines CorporationInventors: Kamal K. Sikka, Krishna R. Tunga
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Publication number: 20200160228Abstract: Embodiments of the invention provide a computer-implemented method of generating individualized strategies for a group of team members pursing a team objective based on an optimized team strategy. A team objective and a plurality of inputs associated with a plurality of team members is received at a strategy engine. A training model is applied to the plurality of inputs from the first plurality of team members to generate a plurality of individualized strategies for the first plurality of team members to achieve the team objective. An optimized team strategy based on the plurality of individualized strategies is generated and the individualized strategies are communicated to each team member wherein each team member pursuing their individualized strategy leads to achieving the team objective.Type: ApplicationFiled: November 15, 2018Publication date: May 21, 2020Inventors: Mahmoud Amin, Zhenxing Bi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Krishna R. Tunga
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Patent number: 10636746Abstract: A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material.Type: GrantFiled: February 26, 2018Date of Patent: April 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamal K. Sikka, Krishna R. Tunga, Hilton T. Toy, Thomas Weiss, Shidong Li, Sushumna Iruvanti
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Patent number: 10622319Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.Type: GrantFiled: July 6, 2017Date of Patent: April 14, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekta Misra, Krishna R. Tunga
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Patent number: 10622275Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.Type: GrantFiled: October 23, 2017Date of Patent: April 14, 2020Assignee: International Business Machines CorporationInventors: Kamal K. Sikka, Krishna R. Tunga
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Publication number: 20200090542Abstract: A computer system interacts with a user with a behavioral state. An activity performed by an entity with a behavioral state is determined. A virtual character corresponding to the entity and performing the determined activity of the entity is generated and displayed. A mental state of the entity responsive to the virtual character is detected. In response to detection of a positive mental state of the entity, one or more natural language terms are provided to the entity corresponding to the activity performed by the virtual character. Embodiments of the present invention further include a method and program product for interacting with a user with a behavioral state in substantially the same manner described above.Type: ApplicationFiled: September 18, 2018Publication date: March 19, 2020Inventors: Lawrence A. Clevenger, Stefania Axo, Leigh Anne H. Clevenger, Krishna R. Tunga, MAHMOUD AMIN, Bryan Gury, Christopher J. Penny, Mark C. Wallen, ZHENXING BI, Yang Liu
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Publication number: 20200066127Abstract: Systems, computer-implemented methods and/or computer program products that facilitate real-time response to defined symptoms are provided. In one embodiment, a computer-implemented method comprises: monitoring, by a system operatively coupled to a processor, a state of an entity; detecting, by the system, defined symptoms of the entity by analyzing the state of the entity; and transmitting, by the system, a signal that causes audio response or a haptic response to be provided to the entity, wherein transmission of the signal that causes the audio response or the haptic response is based on detection of the defined symptoms.Type: ApplicationFiled: December 12, 2018Publication date: February 27, 2020Inventors: Mahmoud Amin, Krishna R. Tunga, Lawrence A. Clevenger, Zhenxing Bi, Leigh Anne H. Clevenger
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Publication number: 20200051447Abstract: Provided are systems, methods, and media for teaching generalization of an object. An example method includes obtaining a set of traits of an object recognized by a person in an input image, in which a subset of traits are traits fixated on by the person when recognizing the object in the input image. Executing a machine learning algorithm to generate a set of generalized images of the object. Each generalized image is generated with at least one trait of being modified, in which the set of generalized images are ordered in a sequence based on proximity of each of the generalized images to the input image. Presenting at least a first generalized image to the person in accordance with the sequence. Modifying the order of the generalized images in the sequence in response to detecting from feedback that the person does not recognize the object in the first generalized image.Type: ApplicationFiled: August 10, 2018Publication date: February 13, 2020Inventors: Krishna R. Tunga, Lawrence A. Clevenger, Stefania Axo, Mark C. Wallen, Yang Liu, Shidong Li, Bryan Gury
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Publication number: 20200035593Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.Type: ApplicationFiled: July 26, 2018Publication date: January 30, 2020Inventors: Anson J. Call, Brian W. Quinlan, Krishna R. Tunga
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Patent number: 10541211Abstract: A method to control warpage in a semiconductor chip package that includes: attaching a semiconductor chip to a semiconductor chip package; attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (CTE) less than that of the substrate on which the chip is assembled; attaching the semiconductor chip package to a laminate substrate; and removing the stiffener.Type: GrantFiled: April 13, 2017Date of Patent: January 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tuhin Sinha, Krishna R. Tunga
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Publication number: 20200013732Abstract: A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material.Type: ApplicationFiled: September 19, 2019Publication date: January 9, 2020Inventors: Kamal K. Sikka, Krishna R. Tunga, Hilton T. Toy, Thomas Weiss, Shidong Li, Sushumna Iruvanti
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Publication number: 20190357843Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.Type: ApplicationFiled: August 6, 2019Publication date: November 28, 2019Inventors: MAHMOUD AMIN, ZHENXING BI, LAWRENCE A. CLEVENGER, LEIGH ANNE H. CLEVENGER, KRISHNA R. TUNGA
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Patent number: 10426400Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.Type: GrantFiled: June 23, 2017Date of Patent: October 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mahmoud Amin, Zhenxing Bi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Krishna R. Tunga
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Publication number: 20190295921Abstract: A method of managing thermal warpage of a laminate which includes: assembling a stiffener and an adhesive on the laminate, the stiffener being a material that has a higher modulus of elasticity than the laminate; applying a force to deform the laminate a predetermined amount; heating the laminate, stiffener and adhesive to a predetermined temperature at which the adhesive cures to bond the stiffener to the laminate; cooling the laminate, stiffener and adhesive to a temperature below the predetermined temperature, the laminate maintaining its deformed shape.Type: ApplicationFiled: March 24, 2018Publication date: September 26, 2019Inventors: Charles L. Arvin, Marcus E. Interrante, Thomas E. Lombardi, Hilton T. Toy, Krishna R. Tunga, Thomas Weiss
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Patent number: 10424527Abstract: An electrical package may comprise a first substrate with a first substrate surface, and a microprocessor chip connected to the first substrate surface. The microprocessor chip may comprise a first chip surface that electrically connects to the first substrate surface, and a second chip surface located opposite the first chip surface. The electrical package may comprise a heat spreader assembly that comprises a lid section and a contact surface thermally connected to the second-chip surface. The electrical package may also comprise a pedestal between the contact surface and the lid section. The pedestal may comprise a first end that is located near the contact surface and a second end that is located near the lid section. The second end may be wider than the first end.Type: GrantFiled: November 14, 2017Date of Patent: September 24, 2019Assignee: International Business Machines CorporationInventors: Kamal K. Sikka, Hilton T. Toy, Krishna R. Tunga, Thomas Weiss
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Patent number: 10420502Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.Type: GrantFiled: November 2, 2017Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mahmoud Amin, Zhenxing Bi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Krishna R. Tunga