Patents by Inventor Krishna Rangasayee
Krishna Rangasayee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8912831Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.Type: GrantFiled: July 5, 2012Date of Patent: December 16, 2014Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, Robert Bielby
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Patent number: 8233577Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.Type: GrantFiled: September 8, 2009Date of Patent: July 31, 2012Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, Robert Bielby
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Apparatus and method for low power routing of signals in a low voltage differential signaling system
Patent number: 7593499Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.Type: GrantFiled: August 4, 2005Date of Patent: September 22, 2009Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, Robert Bielby -
Patent number: 7142557Abstract: Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for a baseband controller, and may include programming instructions for a baseband processor, for configuring the FPGA in accordance therewith. In this manner, a single physical layer may be used with an FPGA to provide a multi-platform application specific standard product (ASSP). This is especially advantageous for providing multi-platform devices for use in countries or applications where one or more standards may be employed.Type: GrantFiled: December 3, 2001Date of Patent: November 28, 2006Assignee: Xilinx, Inc.Inventors: Amit Dhir, Krishna Rangasayee
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Patent number: 6957283Abstract: The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control modules. The physical layer module is preferably a fixed logic component embedded in programmable logic fabric.Type: GrantFiled: July 25, 2001Date of Patent: October 18, 2005Assignee: Xilinx, Inc.Inventors: Amit Dhir, Krishna Rangasayee
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Apparatus and method for low power routing of signals in a Low Voltage Differential Signaling system
Patent number: 6956920Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.Type: GrantFiled: March 21, 2000Date of Patent: October 18, 2005Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, Robert Bielby -
Publication number: 20050084076Abstract: Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for a baseband controller, and may include programming instructions for a baseband processor, for configuring the FPGA in accordance therewith. In this manner, a single physical layer may be used with an FPGA to provide a multi-platform application specific standard product (ASSP). This is especially advantageous for providing multi-platform devices for use in countries or applications where one or more standards may be employed.Type: ApplicationFiled: December 3, 2001Publication date: April 21, 2005Applicant: Xilinx, Inc.Inventors: Amit Dhir, Krishna Rangasayee
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Patent number: 6704889Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.Type: GrantFiled: August 6, 2002Date of Patent: March 9, 2004Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, Alan L. Herrmann
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Patent number: 6625796Abstract: A method of configuring a set of programmable logic devices includes the step of partitioning a programming file into a set of programmable logic device configurations. A set of programmable logic devices are subsequently configured, in parallel, in accordance with the set of programmable logic device configurations.Type: GrantFiled: August 30, 2000Date of Patent: September 23, 2003Assignee: Altera CorporationInventors: Krishna Rangasayee, Nitin Prasad
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Patent number: 6577157Abstract: The present invention provides a programmable pin that may be selectively configured to operate as a signal pin or a power pin. A programmable pin provides increased flexibility in the design of integrated circuit devices. Programmable pins may also be used to provide better performance of the entire integrated circuit device and reduce noise in the pins of the integrated circuit device that are signal pins. The programmable pin may also include the function of retaining the last asserted state on the pin. Memory provides further functionality and flexibility in the design of integrated circuit devices.Type: GrantFiled: November 5, 1998Date of Patent: June 10, 2003Assignee: Altera CorporationInventors: Sammy S. Y. Cheung, Krishna Rangasayee
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Publication number: 20030023762Abstract: The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control modules. The physical layer module is preferably a fixed logic component embedded in programmable logic fabric.Type: ApplicationFiled: July 25, 2001Publication date: January 30, 2003Applicant: Xilinx, Inc.Inventors: Amit Dhir, Krishna Rangasayee
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Publication number: 20020194543Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.Type: ApplicationFiled: August 6, 2002Publication date: December 19, 2002Applicant: Altera Corporation, A Delaware CorporationInventors: Kerry Veenstra, Krishna Rangasayee, Alan L. Herrmann
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Patent number: 6472903Abstract: In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and—to the extent that each such scheme requires a reference voltage—the same reference voltage requirements.Type: GrantFiled: August 4, 1999Date of Patent: October 29, 2002Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, John E. Turner
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Patent number: 6460148Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.Type: GrantFiled: June 21, 2001Date of Patent: October 1, 2002Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, Alan L. Herrmann
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Patent number: 6404225Abstract: An integrated circuit operable in a plurality of switching modes is disclosed. The integrated circuit includes a plurality of direct connectors and a programmable switch unit operable in a plurality of switching modes. The programmable switch unit has a plurality of bi-directional I/O ports selectively connected by way of programmable switch unit internal connectors. The integrated circuit also includes a programmable function unit directly connected to the programmable switch unit by way of the direct connectors. The programmable function unit is programmable configured to operate as required by a selected one of the plurality of switching modes. As required by the selected one of the plurality of switching modes, the programmable function unit directs the programmable switch unit to form internal connections using the programmable switch unit internal connectors such that the programmable switch unit passes signals between selected portions of the plurality of bi-directional I/O ports.Type: GrantFiled: November 2, 2000Date of Patent: June 11, 2002Assignee: Altera CorporationInventor: Krishna Rangasayee
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Patent number: 6377069Abstract: In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and—to the extent that each such scheme requires a reference voltage—the same reference voltage requirements.Type: GrantFiled: May 2, 2001Date of Patent: April 23, 2002Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, John E. Turner
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Patent number: 6363505Abstract: A circuit for programmably grounding (or coupling to the positive rail) unused outputs to improve noise immunity of the circuit. The circuit of the present invention achieves, for example, programmable grounding of an output via already existing test signal paths, without introducing delays in speed critical output signal paths.Type: GrantFiled: June 1, 1999Date of Patent: March 26, 2002Assignee: Altera CorporationInventors: W. Bradley Vest, Krishna Rangasayee
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Patent number: 6356108Abstract: An integrated circuit capable of efficiently storing data words of varying length is disclosed. The inventive integrated circuit can be a programmable logic device that includes a plurality of configurable memory array blocks. The integrated circuit includes a control circuit that characterizes data to be stored and based upon that characterization provides control signals to direct connectors. The direct connectors then directly connect selected configurable memory array blocks when a single memory array block could not accommodate the data to be stored.Type: GrantFiled: March 1, 2001Date of Patent: March 12, 2002Assignee: Altera CorporationInventor: Krishna Rangasayee
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Publication number: 20010037477Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.Type: ApplicationFiled: June 21, 2001Publication date: November 1, 2001Inventors: Kerry Veenstra, Krishna Rangasayee, Alan L. Herrmann
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Patent number: 6300790Abstract: In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and—to the extent that each such scheme requires a reference voltage—the same reference voltage requirements.Type: GrantFiled: August 4, 1999Date of Patent: October 9, 2001Assignee: Altera CorporationInventors: Kerry Veenstra, Krishna Rangasayee, John E. Turner