Abstract: An integrated circuit capable of efficiently storing data words of varying length is disclosed. The inventive integrated circuit can be a programmable logic device that includes a plurality of configurable memory array blocks. The integrated circuit includes a control circuit that characterizes data to be stored and based upon that characterization provides control signals to direct connectors. The direct connectors then directly connect selected configurable memory array blocks when a single memory array block could not accommodate the data to be stored.

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.

Abstract: An integrated circuit capable of efficiently storing data words of varying length is disclosed. The inventive integrated circuit can be a programmable logic device that includes a plurality of configurable memory array blocks. The integrated circuit includes a control circuit that characterizes data to be stored and based upon that characterization provides control signals to direct connectors. The direct connectors then directly connect selected configurable memory array blocks when a single memory array block could not accommodate the data to be stored.

Abstract: The present invention integrates a phase lock loop (PLL) with a programmable logic device (PLD) to realize a flexible PLD with a variety of clocking options. The present invention generates multiple clock frequencies internally to a programmable logic device using a single reference clock input. The programmer can dynamically change the functionality of the programmable logic device. As a result, a “virtual hardware device” is realized. The ability to change the frequency of operation also dynamically offers a tremendous advantage to users of reconfigurable computing.

Abstract: A programmable logic device having content addressable memory is disclosed. In a preferred embodiment, the programmable logic device includes reconfigurable dual mode memory suitable for operating as a content addressable memory in a first mode and a random access memory in a second mode is disclosed. Mode control switch circuitry may be provided to selectively enable a user to configure the dual mode memory as either content addressable memory or random access memory.

Abstract: Embedding a logic analyzer in a programmable logic device allows signals to be captured both before and after a trigger condition (breakpoint). A logic analyzer embedded within a PLD captures and stores logic signals. It unloads these signals for viewing on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, a breakpoint, total number of samples to be stored, number of samples to be captured after the breakpoint occurs, and a system clock signal. The EDA tool automatically inserts the logic analyzer into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool commands the embedded logic analyzer to run. Signals are stored continuously while running in a ring buffer RAM memory. Once the breakpoint occurs, more samples are captured if desired, in addition to those signals captured before breakpoint.

Abstract: An integrated circuit contains circuitry to operate in such a fashion to reduce output noise when switching output circuits from a programming mode to a user mode. In an implementation, the integrated circuit (125) is configurable in the programming mode with user configuration data. In the user mode, the integrated circuit will operate with the functionality as defined by the user during the programming mode. When switching from the programming mode to the user mode, each output (210) of the integrated circuit will switch to its user mode value. In order to minimize switching noise, the outputs are released to their user mode values not all at the same time.

Abstract: An electronic device includes an Erasable Programmable Read-Only Memory (EPROM), a programmable logic device connected to the EPROM, and a single package enclosing the EPROM and the programmable logic device. The electronic device provides combined functionality that allows the EPROM to store configuration data for a programmable logic device, a Static Random Access Memory (SRAM), or an external programmable logic device, while the programmable logic device is configured to implement another function, such as a Joint Test Access Group interface function, an address decoder function, or a state machine function.

Abstract: An integrated circuit operable in a plurality of switching modes is disclosed. The integrated circuit includes a plurality of direct connectors and a programmable switch unit operable in a plurality of switching modes. The programmable switch unit has a plurality of bi-directional I/O ports selectively connected by way of programmable switch unit internal connectors. The integrated circuit also includes a programmable function unit directly connected to the programmable switch unit by way of the direct connectors. The programmable function unit is programmably configured to operate as required by a selected one of the plurality of switching modes. As required by the selected one of the plurality of switching modes, the programmable function unit directs the programmable switch unit to form internal connections using the programmable switch unit internal connectors such that that programmable switch unit passes signals between selected portions of the plurality of bi-directional I/O ports.

Abstract: A method of programming and verifying a macroscale based architecture in a field programmable logic device includes the step of selecting a flip-flop. The flip-flop contains a programmable address that accepts a sequence of instructions. A Switch Controller then selectably enables either one of two banks of switches. If the first bank of switches is selected, the programming operation is selected. If the second bank of switches is enabled, the verification operation is selected. The verification operation includes the step of automatically incrementing a base address through a set of incremented addresses. For each incremented address produced by the incrementing step, a margin low operation is performed with a Level Tester Array and a margin high operation is performed with a Level Tester Array. Thus, unlike the prior art, margin operations with the present invention are performed without using a macrocell scan register.

Abstract: A programmable logic device has buffers that may be selectively programmed for Schmitt-triggered and threshold-triggered operation. The programmable Schmitt-triggered buffers are connected to circuit nodes that are sensitive to noisy environments. The programmable threshold-triggered buffers are connected to circuit nodes that have critical timing requirements.

Abstract: An integrated circuit capable of efficiently storing data words of varying length is disclosed. The inventive integrated circuit can be a programmable logic device that includes a plurality of configurable memory array blocks. The integrated circuit includes a control circuit that characterizes data to be stored and based upon that characterization provides control signals to direct connectors. The direct connectors then directly connect selected configurable memory array blocks when a single memory array block could not accommodate the data to be stored.

Abstract: A programmable logic device architecture incorporating a cross-bar switch is disclosed. In a preferred embodiment, a plurality of logic cells is programmably interconnected to form an array of logic cells capable of implementing complex logic functions. A user selectable cross-bar switch block having dedicated programmable connectors is coupled to the array of logic cells by way of a mode control circuit switch. The mode control circuit switch is arranged to couple the dedicated cross-bar switch block to the array of logic cells in a first mode and to de-couple the cross-bar switch block from the array of logic blocks in a second mode.

Abstract: A programmable logic device having content addressable memory is disclosed. In a preferred embodiment, the programmable logic device includes reconfigurable dual mode memory suitable for operating as a content addressable memory in a first mode and a random access memory in a second mode is disclosed. Mode control switch circuitry may be provided to selectively enable a user to configure the dual mode memory as either content addressable memory or random access memory.

Abstract: A programmable logic device having content addressable memory is disclosed. In a preferred embodiment, the programmable logic device includes reconfigurable dual mode memory suitable for operating as a content addressable memory in a first mode and a random access memory in a second mode is disclosed. Mode control switch circuitry may be provided to selectively enable a user to configure the dual mode memory as either content addressable memory or random access memory.

Abstract: A method and apparatus for generating an asynchronously clocked signal in a synchronously clocked programmable device is described. A programmable logic device having synchronously clocked or product term clocked registers receives an input signal and an event signal. The input signal and the event signal can be any externally or internally generated signals. The event signal signifies the occurrence of a particular event by transitioning from one signal state to another. The input signal is asynchronously clocked through the synchronously clocked PLD without utilizing the synchronously clocked or product term clocked registers. The input signal is asynchronously clocked in response to an edge transition of the event signal. The edge transition of the event signal being either a failing edge or a rising edge.