Abstract: A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

Abstract: A wafer cutting apparatus which includes a wafer saw, a detector, and a control unit. The detector detects a variable of a wafer being sawed. The control unit utilizes the variable to control the saw.

Abstract: A method of passivating an integrated circuit (IC) is provided. An insulating layer is formed onto the IC. An adhesion layer is formed onto a surface of the insulating layer by treating the surface of the insulating layer with a gas and gas plasma. A first passivation layer is formed upon the adhesion layer, the first passivation layer and the gas and gas plasma including at least one common chemical element.

Abstract: A method of testing an integrated circuit device including depositing a solder bump on a surface of a bond pad on an integrated circuit device, heat treating the solder bump, and testing the integrated circuit device by probing the solder bump.

Abstract: An integrated circuit (IC) is provided. The IC includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer and metal layer form a die active area. The IC further includes a guard ring, enclosing the die active area. The guard ring has zig-zag shaped portions at corners thereof.

Abstract: A method of exposing a bond pad includes: providing an integrated circuit having a bond pad, a first passivation layer overlying an area portion of the bond pad, and a second passivation layer overlying the first passivation layer; removing a portion of the second passivation layer above the area portion of the bond pad exposing an area of the first passivation layer; curing the second passivation; and etching a portion of the exposed area of the first passivation layer to expose the top surface of the bond pad. A method of coupling an integrated circuit chip to a chip package is also disclosed as is a method of probing the bond pads of an integrated circuit. A probe card is further disclosed, including a probe assembly coupled to a printed circuit board, the probe assembly having a sloped sidewall portion with a plurality of probing beams extending from the sidewall portion.

Abstract: An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

Abstract: An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit further includes a planar passivating layer formed upon the terminal dielectric layer.

Abstract: A wafer testing rig includes a stand, a first contact component, a second contact component and a biasing device. The first contact component is mounted to the stand. The second contact component is mounted to the stand for movement towards and away from the first contact component. The first and second contact components are shaped so that a wafer, when located between the contact components, is deflected into a dome shape when the second contact component is moved towards the first contact component. The biasing device is operable to move the second contact component towards and away from the first contact component. An electrical tester is provided to test the wafer.

Abstract: A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

Abstract: An integrated circuit passivation layer including a first passivation layer portion of silicon nitride treated with nitrous oxide and a second passivation layer portion of polyimide. Also, a method of passivating an integrated circuit wafer including depositing a first passivation layer over the top surface of an integrated circuit wafer having a scribe street area between adjacent integrated circuit device portions, depositing a second passivation layer over the first passivation layer, and patterning the first passivation layer and the second passivation layer to expose the scribe street area.

Abstract: An integrated circuit (IC) is provided. The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further includes a terminal metal layer (TML) formed upon the dielectric layer. The dielectric layer and the TML form a die active area. The TML has formed therein a plurality of spaced locking structures. The plurality of space locking structures are electrically isolated therebetween. Each locking structure is formed outside the die active area. The IC further includes a passivation layer adhering to the locking structures.

Abstract: The present invention provides in one embodiment thereof an integrated circuit (IC) that includes silicon substrate. The integrated circuit includes a plurality of dielectric and metal layers formed upon the silicon substrate. The plurality of dielectric and metal layers form a die active area. The metal have formed therein a first guard wall surrounding the die active area. The metal layers further have formed therein a second segmented guard wall. The segmented guard wall surrounds and staples the plurality of metal layers. The IC also includes a passivation layer adhering to the first and the segmented guard walls.

Abstract: The present invention provides in one embodiment thereof an integrated circuit (IC). The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further includes a terminal metal layer (TML) formed upon the dielectric layer. The dielectric layer and the TML form a die active area. The IC also includes a first guard ring formed out of the TML. The first guard encloses the die active area. Furthermore the IC includes a second guard ring formed out of the TML. The second guard ring encloses the first guard ring.

Abstract: A method of fabricating an electrically programmable fuse buried under quartz and layers of polyimide with a specific structure to enhance its "thermal" capabilities. The fuse is designed to "blow" and cool off quickly so as not to cause damage to areas above and surrounding the fuse. A passivation layer is added above the fuse to act as a heat sink and absorb and redistribute the heat generated from one localized area to a broader and cooler area. The materials used for the fuse and the heat sink are selected to be compatible with both oxide and polyimide personalization schemes. Modeling of the fuse enables optimizing the characteristics of the fuse, particularly to transmit to the surface of the passivation layer the thermal wave created during programming of the fuse.

Abstract: A method of fabricating a noise immune fuse having sub-micron dimensions which can be programmed by an electrically and thermally synchronized event. The fuse includes a pair of fuse links in close proximity of each other, a layer of thermally conductive and electrically insulating material thermally coupling the two links forming the pair, and means for programming the first link by prompting the second link to gate the energy transfer between the links via the coupling layer. By combining thermal and electrical pulses to perform the programming function, the reliability of the fuse structure is greatly enhanced when compared to that of a single element fuse.

Abstract: An electrically programmable fuse buried under quartz and layers of polyimide with a specific structure to enhance its "thermal" capabilities. The fuse is designed to "blow" and cool off quickly so as not to cause damage to areas above and surrounding the fuse. A passivation layer is added above the fuse to act as a heat sink and absorb and redistribute the heat generated from one localized area to a broader and cooler area. The materials used for the fuse and the heat sink are selected to be compatible with both oxide and polyimide personalization schemes. Modeling of the fuse enables optimizing the characteristics of the fuse, particularly to transmit to the surface of the passivation layer the thermal wave created during programming of the fuse.

Abstract: A measurement technique and instrument using rectangular pulse trains of differing repetition rates and synchronously operated lock-in amplifiers to reject electrical noise and capture changes in resistance and capacitance of an electrical element even during a short electrical pulse applied thereto or in the presence of high levels of electrical noise. Particular applications are for electrical programming of fuses and repair of conductors by material deposition.

Abstract: A noise immune fuse having sub-micron dimensions which can be programmed by an electrically and thermally synchronized event. The fuse includes a pair of fuse links in close proximity of each other, a layer of thermally conductive and electrically insulating material thermally coupling the two links forming the pair, and means for programming the first link by prompting the second link to gate the energy transfer between the links via the coupling layer. By combining thermal and electrical pulses to perform the programming function, the reliability of the fuse structure is greatly enhanced when compared to that of a single element fuse.

Abstract: An improved antifuse uses metal penetration of either a P-N diode junction or a Schottky diode. The P-N junction, or Schottky diode, is contacted by a diffusion barrier such as TiN, W, Ti-W alloy, or layers of Ti and Cr, with a metal such as Al. Al-CU alloy, Cu, Au, or Ag on top of the diffusion barrier. When this junction is stressed with voltage pulse producing a high current density, severe joule heating occurs resulting in metal penetration of the diffusion barrier and the junction. The voltage drop across the junction decreases by about a factor of ten after the current stress and is stable thereafter. Alternatively, a shallow P-N junction in a silicon substrate is contacted by a layer of metal that forms a silicide, such as Ti, Cr, W, Mo, or Ta. Stressing the junction with a voltage pulse to produce a high current density results in the metal penetrating the junction and reacting with the substrate to form a silicide.