Abstract: The application is directed towards facilitating the debugging of suspected errors in a proprietary component when the proprietary component is incorporated into a larger electronic design. Various implementations provide for the generation of a reference model for an integrated circuit design, where the reference model includes the proprietary component and sufficient information about the rest of the design to allow for the debugging of the proprietary component over a period of verification where the error in the proprietary component is suspected.

Abstract: Aspects of the invention relate to techniques for adaptive clock management in emulation. A clock suspension request signal, indicating when a suspension of design clock signals in an emulator is needed, is generated based on activity status information of the emulator with one or more emulator resources such as software environment. A clock suspension allowance signal, indicating whether a suspension of design clock signals is permitted considering dynamic targets in the emulator, is generated based on slack information related to one or more clock signals associated with one or more dynamic targets of the emulator. Based on the clock suspension request signal and the clock suspension allowance signal, a clock suspension signal is generated for enabling temporary design clock suspensions.

Abstract: Aspects of the invention relate to techniques for dynamic control of design clock generation in emulation. A circuit design for verification is analyzed to determine one or more clock-enabling functions for a specific clock signal. Logic for generating a clock status signal based on the one or more clock-enabling signals is then determined. The clock status signal is employed to control clock generation in an emulation system for emulating the circuit design.