Patents by Inventor Kristin Schupke
Kristin Schupke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8835298Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni?/Pt layer at a temperature of 130° C.Type: GrantFiled: March 8, 2012Date of Patent: September 16, 2014Assignee: GlobalFoundries Inc.Inventors: Sivakumar Kumarasamy, Clemens Fitz, Markus Lenski, Jochen Poth, Kristin Schupke
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Patent number: 8835318Abstract: Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.Type: GrantFiled: March 8, 2012Date of Patent: September 16, 2014Assignee: GlobalFoundries Inc.Inventors: Clemens Fitz, Jochen Poth, Kristin Schupke
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Publication number: 20130234335Abstract: Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.Type: ApplicationFiled: March 8, 2012Publication date: September 12, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Clemens Fitz, Jochen Poth, Kristin Schupke
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Publication number: 20130234213Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C.Type: ApplicationFiled: March 8, 2012Publication date: September 12, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Sivakumar KUMARASAMY, Clemens Fitz, Markus Lenski, Jochen Poth, Kristin Schupke
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Patent number: 7863149Abstract: In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).Type: GrantFiled: September 9, 2005Date of Patent: January 4, 2011Assignee: Qimonda AGInventors: Srivatsa Kundalgurki, Peter Moll, Dirk Manger, Kristin Schupke, Till Schloesser
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Patent number: 7615444Abstract: A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads; depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.Type: GrantFiled: June 29, 2006Date of Patent: November 10, 2009Assignee: Qimonda AGInventors: Odo Wunnicke, Peter Moll, Kristin Schupke
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Patent number: 7479461Abstract: A method for etching Si anisotropically uses a solution containing NH4F and HF.Type: GrantFiled: September 17, 2004Date of Patent: January 20, 2009Assignees: Infineon Technologies AG, Nanya Technology CorporationInventors: Teng-Wang Huang, Kristin Schupke
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Publication number: 20080230839Abstract: The invention is related to a method of producing a semiconductor structure comprising the steps of: fabricating a gate stack structure and oxidizing at least a portion of the gate stack structure's sidewalls, wherein the step of oxidizing is carried out at a temperature below 500° C. using a process gas which comprises oxygen radicals.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Inventors: Joern Regul, Joerg Radecker, Olaf Storbeck, Kristin Schupke, Tobias Mono
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Publication number: 20080009139Abstract: A structure in a substrate for the manufacturing of a semiconductor device, wherein a first material and at least one second material are to be etched by at least one etching medium, wherein the at least one second material has a higher etch rate for the at least one etching medium relative to the first material. The at least one second material occupies a space which is at least at one side adjacent to the first material so that an additional etching access to the first material is prepared when at least one etching medium etches the first and the second material.Type: ApplicationFiled: July 5, 2006Publication date: January 10, 2008Inventors: Thomas Hecht, Kristin Schupke, Kevin Bauer, Steffen Mueller, Henry Bernhardt
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Publication number: 20080003740Abstract: A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads; depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.Type: ApplicationFiled: June 29, 2006Publication date: January 3, 2008Inventors: Odo Wunnicke, Peter Moll, Kristin Schupke
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Publication number: 20070212849Abstract: The present invention relates to a method of fabricating a groove-like structure in a semiconductor device including etching a trench in a substrate, filling the trench with a spin-on-glass liquid forming a spin-on-glass liquid layer containing a solvent, baking the spin-on-glass liquid layer in order to remove the solvent and forming a baked layer, etching the baked layer to a predetermined depth using an etchant that provides a larger etch rate with regard to silicon than with regard to silicon nitride or silicon oxide, and, after etching the baked layer, annealing the remaining baked layer and forming a spin-on-glass oxide layer inside the trench.Type: ApplicationFiled: March 10, 2006Publication date: September 13, 2007Inventors: Frank Ludwig, Kimberly Wilson, Arabinda Das, Hans-Peter Sperlich, Andreas Klipp, Kristin Schupke
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Publication number: 20070141850Abstract: A semiconductor product includes an exposed Hafnium-containing layer. The Hafnium-containing layer is treated with a solution that includes a low ionic strength organic substance.Type: ApplicationFiled: November 30, 2006Publication date: June 21, 2007Inventors: Audrey Dupont, Kristin Schupke, Stefan Jakschik, Alejandro Avellan
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Publication number: 20070012662Abstract: It is one object to devise a solution which is suitable for a wet treatment of Hafnium containing high-k materials. Furthermore, it is an object to devise a use of this solution in the field of semiconductor device manufacturing. It is also an objective of the invention to devise a process to this aim.Type: ApplicationFiled: July 18, 2005Publication date: January 18, 2007Inventors: Audrey Dupont, Kristin Schupke, Stefan Jakschik, Alejandro Avellan
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Patent number: 7078748Abstract: A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned.Type: GrantFiled: June 14, 2004Date of Patent: July 18, 2006Assignees: Infineon Technologies AG, Nanya Technology CorporationInventors: Matthias Goldbach, Frank Jakubowski, Ralf Koepe, Chao-Wen Lay, Kristin Schupke, Michael Schmidt, Cheng-Chih Huang
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Publication number: 20060079049Abstract: In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).Type: ApplicationFiled: September 9, 2005Publication date: April 13, 2006Inventors: Srivatsa Kundalgurki, Peter Moll, Dirk Manger, Kristin Schupke, Till Schloesser
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Patent number: 7018781Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.Type: GrantFiled: March 29, 2004Date of Patent: March 28, 2006Assignee: Infineon Technologies, AGInventors: Hans-Georg Fröhlich, Oliver Genz, Werner Graf, Stefan Gruss, Matthias Handke, Percy Heger, Lars Heineck, Antje Laessig, Alexander Reb, Kristin Schupke, Momtchil Stavrev, Mirko Vogt
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Patent number: 7005723Abstract: In a method of producing a bipolar transistor, a semiconductor substrate having a substrate surface is provided. A base-terminal layer for providing a base terminal is formed on the substrate surface, and an emitter window having a wall area is formed in the base-terminal layer. A first spacing layer is formed on the wall area of the emitter contact window, and a recess is etched into the substrate within a window specified by the first spacing layer. A base layer contacted by outdiffusion from the base-terminal layer is formed in the recess of the emitter window, and a second spacing layer is formed on the first spacing layer and on the base layer. The second spacing layer is structured for the purpose of specifying a planar terminal pad on the base layer, and an emitter layer is formed on the planar terminal pad.Type: GrantFiled: January 23, 2004Date of Patent: February 28, 2006Assignee: Infineon Technologies AGInventors: Armin Tilke, Kristin Schupke
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Publication number: 20050275046Abstract: A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned.Type: ApplicationFiled: June 14, 2004Publication date: December 15, 2005Inventors: Matthias Goldbach, Frank Jakubowski, Ralf Koepe, Chao-Wen Lay, Kristin Schupke, Michael Schmidt, Cheng-Chih Huang
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Publication number: 20050221620Abstract: The invention relates to a process for etching at least one substrate, in particular at least one silicon wafer for the fabrication of DRAM memory chips. The process comprising at least one substrate, for a first etching step, is arranged for a predetermined time in a first vessel containing a first etchant, then at least one substrate, for a first rinsing step, is arranged for a predetermined time in a second vessel containing a first rinsing agent, the first rinsing agent containing at least one wetting agent, and then at least one substrate, for a second etching step, is arranged for a predetermined time in a third vessel containing a second etchant.Type: ApplicationFiled: March 31, 2004Publication date: October 6, 2005Inventors: Teng-Wang Huang, Kristin Schupke
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Publication number: 20050191564Abstract: A method for producing a liner mask on a semiconductor structure is disclosed. The method may include providing an amorphous liner layer (55) on the top side (OS;OS?) of the semiconductor structure, annealing the amorphous liner layer (55) to increase the crystallisation and generate a semi-crystalline liner layer (55); implanting (I1) extrinsic ions in a subregion (55a) of the semi-crystalline liner layer (55) to decrease the etching rate of the subregion (55a) and create an etch selectivity between the to the subregion (55a) complementary subregion (55b) and the subregion (55a) in the predetermined etchant; and selectively removing of the to the subregion (55a) complementary subregion (55b) opposite to the subregion (55a) in a etching step in the predetermined etchant for completing the liner mask.Type: ApplicationFiled: February 27, 2004Publication date: September 1, 2005Inventors: Teng-Wang Huang, Kristin Schupke, Hai-Han Hung