Abstract: A method for etching Si anisotropically uses a solution containing NH4F and HF.

Abstract: In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconduct

Abstract: A semiconductor component has a cavity formed in a monocrystalline silicon substrate. The wall of the cavity is covered by a cover layer, at least in an upper collar region, and a covering layer is then applied to the surface of the silicon substrate using a selective epitaxial growth method. The cavity is thereby covered in the process. The method is physically simple and can be carried out cost-effectively. In particular, the described method can be used in order to cover a trench prior to high-temperature processes during the production of a DRAM memory, and to open the trench once again after the high-temperature processes, in order to provide a trench capacitor.

Abstract: In a method of producing a bipolar transistor, a semiconductor substrate having a substrate surface is provided. A base-terminal layer for providing a base terminal is formed on the substrate surface, and an emitter window having a wall area is formed in the base-terminal layer. A first spacing layer is formed on the wall area of the emitter contact window, and a recess is etched into the substrate within a window specified by the first spacing layer. A base layer contacted by outdiffusion from the base-terminal layer is formed in the recess of the emitter window, and a second spacing layer is formed on the first spacing layer and on the base layer. The second spacing layer is structured for the purpose of specifying a planar terminal pad on the base layer, and an emitter layer is formed on the planar terminal pad.

Abstract: A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon.

Abstract: A method for fabricating a trench capacitor for a semiconductor memory includes forming a masking layer in a trench that is disposed in a substrate. Nanocrystallites, which are used to pattern the masking layer, are deposited on the masking layer. Microtrenches are etched into the substrate in a lower region of the trench by the patterned masking layer. The microtrenches form a roughened trench sidewall. As a result, the outer capacitor electrode is formed with a larger surface area, allowing the trench capacitor to have a higher capacitance.

Abstract: A method for etching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon.

Abstract: A semiconductor component has a cavity formed in a monocrystalline silicon substrate. The wall of the cavity is covered by a cover layer, at least in an upper collar region, and a covering layer is then applied to the surface of the silicon substrate using a selective epitaxial growth method. The cavity is thereby covered in the process. The method is physically simple and can be carried out cost-effectively. In particular, the described method can be used in order to cover a trench prior to high-temperature processes during the production of a DRAM memory, and to open the trench once again after the high-temperature processes, in order to provide a trench capacitor.

Abstract: The present invention provides a method for fabricating a semiconductor component having a substrate (1) and a dielectric layer (70) provided on or in the substrate (1), the dielectric layer (7) being deposited in alternating self-limiting monolayer form, in the form of at least two different precursors, by means of an ALD process. There is provision for conditioning of the surface of the substrate (1) prior to the deposition of a first monolayer of a first precursor with respect to a reactive ligand of the first precursor.

Abstract: A method for fabricating a trench capacitor for a semiconductor memory includes forming a masking layer in a trench that is disposed in a substrate. Nanocrystallites, which are used to pattern the masking layer, are deposited on the masking layer. Microtrenches are etched into the substrate in a lower region of the trench by the patterned masking layer. The microtrenches form a roughened trench sidewall. As a result, the outer capacitor electrode is formed with a larger surface area, allowing the trench capacitor to have a higher capacitance.