Patents by Inventor Ku-Feng Yang

Ku-Feng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151367
    Abstract: Semiconductor structures and method of forming the same are provided. A method according to the present disclosure includes providing an intermediate structure that includes an opening, conformally depositing a metal liner over the opening, depositing a dummy fill material over the metal liner, recessing the dummy fill material such that a portion of the metal liner is exposed, removing the exposed portion of the metal liner, removing the recessed dummy fill material, and after the removing of the recessed dummy fill material, depositing a metal fill layer over the opening.
    Type: Application
    Filed: March 8, 2024
    Publication date: May 8, 2025
    Inventors: Kai-Chieh Yang, Chun-Yu Liu, Wei-Yen Woon, Ku-Feng Yang, Szuya Liao
  • Publication number: 20250140639
    Abstract: The present disclosure provides an integrated circuit (IC) structure in accordance with some embodiments. The IC structure includes a circuit structure having semiconductor devices formed on a first substrate, an interconnect structure over the semiconductor devices; and a thermal dissipation structure formed on a second substrate. The second substrate is boned to the circuit structure such that the thermal dissipation structure is interposed between the first and second substrates. The thermal dissipation structure includes a diamond-like carbon (DLC) layer. The DLC layer includes a bottom portion having large grain sizes and a top portion having fine DLC grain sizes.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 1, 2025
    Inventors: Che Chi Shih, Ku-Feng Yang, Szuya Liao
  • Publication number: 20250132150
    Abstract: A method includes forming a first de-bond structure over a first substrate, where forming the first de-bond structure includes depositing a first de-bond layer over the first substrate, depositing a first silicon layer over the first de-bond layer, depositing a second de-bond layer over the first silicon layer, and depositing a second silicon layer over the second de-bond layer, epitaxially growing a first multi-layer stack over the first de-bond structure, bonding the first multi-layer stack to a second multi-layer stack, and performing a first laser annealing process to ablate the first silicon layer and portions of the first de-bond layer and the second de-bond layer in order to de-bond the first substrate from the first multi-layer stack.
    Type: Application
    Filed: February 20, 2024
    Publication date: April 24, 2025
    Inventors: Che Chi Shih, Chun-Yu Liu, James June Fan Hsu, Ku-Feng Yang, Szuya Liao
  • Publication number: 20250125262
    Abstract: The present disclosure relates to an integrated circuit (IC) structure. The IC structure includes a semiconductor device having a frontside and a backside opposite the frontside. A first interconnect structure disposed on the frontside of the semiconductor device. The first interconnect structure comprises a first dielectric structure having a plurality of inter-level dielectric (ILD) layers. A second dielectric structure disposed on the backside of the semiconductor device. The second dielectric structure comprises a first high thermal conductivity layer having a thermal conductivity greater than that of the ILD layers.
    Type: Application
    Filed: February 29, 2024
    Publication date: April 17, 2025
    Inventors: Che Chi Shih, Tsung-Kai Chiu, Ku-Feng Yang, Wei-Yen Woon, Szuya Liao
  • Patent number: 12278203
    Abstract: A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20250118619
    Abstract: A method includes forming a bonding structure that contains thermal conductive vias (also termed as thermal vias, thermal conductive pillars, or thermal pillars) on a semiconductor structure. The thermal vias, with material thermal conductivity greater than about 10 W/m·K, are embedded in the bonding structure that provides a quick dissipation path of heat from thermal hotspot regions into a substrate.
    Type: Application
    Filed: March 12, 2024
    Publication date: April 10, 2025
    Inventors: Yung-Ta Chen, Kuan-Kan Hu, Chun-Yu Liu, Che Chi Shih, Ku-Feng Yang, Szuya Liao
  • Publication number: 20250095997
    Abstract: A method of forming a semiconductor device includes depositing a target metal layer in an opening. Depositing the target metal layer comprises performing a plurality of deposition cycles. An initial deposition cycle of the plurality of deposition cycles comprises: flowing a first precursor in the opening, flowing a second precursor in the opening after flowing the first precursor, and flowing a reactant in the opening. The first precursor attaches to upper surfaces in the opening, and the second precursor attaches to remaining surfaces in the opening. The first precursor does not react with the second precursor, and the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor.
    Type: Application
    Filed: March 11, 2024
    Publication date: March 20, 2025
    Inventors: Kai-Chieh Yang, Kuan-Kan Hu, Wei-Yen Woon, Ku-Feng Yang, Szuya Liao
  • Patent number: 12237284
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an interconnect structure disposed over a semiconductor substrate, contact pads disposed on the interconnect structure, a dielectric structure disposed on the interconnect structure and covering the contact pads, bonding connectors covered by the dielectric structure and landing on the contact pads, and a dummy feature covered by the dielectric structure and laterally interposed between adjacent two of the bonding connectors. Top surfaces of the bonding connectors are substantially coplanar with a top surface of the dielectric structure, and the bonding connectors are electrically coupled to the interconnect structure through the contact pads.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 12227867
    Abstract: A plating apparatus includes a workpiece holder, a plating bath, and a clamp ring. The plating bath is underneath the workpiece holder. The clamp ring is connected to the workpiece holder. The clamp ring includes channels communicating an inner surface of the clamp ring and an outer surface of the clamp ring.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
  • Publication number: 20250031419
    Abstract: Method to form low-contact-resistance contacts to source/drain features are provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, selectively depositing a first silicide layer on the surface of the p-type source/drain feature while the surface of the n-type source/drain feature is substantially free of the first silicide layer, depositing a metal layer on the first silicide layer and the surface of the n-type source/drain feature, and depositing a second silicide layer over the metal layer. The selectively depositing includes passivating the surface of the surface of the n-type source/drain features with a self-assembly layer, selectively depositing the first silicide layer on the surface of the p-type source/drain feature, and removing the self-assembly layer.
    Type: Application
    Filed: July 17, 2023
    Publication date: January 23, 2025
    Inventors: Kuan-Kan Hu, Po-Chin Chang, Olivia Pei-Hua Lee, Ku-Feng Yang, Sung-Li Wang, Szuya Liao
  • Publication number: 20250031413
    Abstract: Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che Chi SHIH, Jhih-Rong HUANG, Han-Yu LIN, Ku-Feng YANG, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20250006561
    Abstract: Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Kan HU, Che Chi SHIH, Ku-Feng YANG, Szuya LIAO
  • Publication number: 20240413039
    Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a semiconductor substrate, a high-Kappa dielectric layer disposed on the semiconductor substrate, a first plurality of nanostructures disposed over the high-Kappa dielectric layer, a middle dielectric layer disposed over the first plurality of nanostructures, a second plurality of nanostructures over the middle dielectric layer, a first gate structure wrapping around the first plurality of nanostructures, a second gate structure wrapping around the second plurality of nanostructures. The high-Kappa dielectric layer includes metal nitride, metal oxide, silicon carbide, graphene, or diamond.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 12, 2024
    Inventors: Che Chi Shih, Wei-Yen Woon, Ku-Feng Yang, Szuya Liao
  • Publication number: 20240387449
    Abstract: A method includes putting a first package component into contact with a second package component. The first package component comprises a first dielectric layer including a first dielectric material, and the first dielectric material is a silicon-oxide-based dielectric material. The second package component includes a second dielectric layer including a second dielectric material different from the first dielectric material. The second dielectric material comprises silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof. An annealing process is performed to bond the first dielectric layer to the second dielectric layer.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Ku-Feng Yang, Ming-Tsu Chung
  • Publication number: 20240379748
    Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Kuan-Kan Hu, Han-De Chen, Ku-Feng Yang, Chen-Fong Tsai, Chi On Chui, Szuya Liao
  • Publication number: 20240371804
    Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
  • Publication number: 20240363411
    Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Ming-Tsu Chung, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 12131954
    Abstract: A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed. A contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.
    Type: Grant
    Filed: December 6, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che Chi Shih, Hsin Yang Hung, Ku-Feng Yang, Wei-Yen Woon, Szuya Liao
  • Patent number: 12132016
    Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yu Tsai, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 12132079
    Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.
    Type: Grant
    Filed: December 21, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Kan Hu, Han-De Chen, Ku-Feng Yang, Chen-Fong Tsai, Chi On Chui, Szuya Liao