Abstract: A method includes forming a bonding structure that contains thermal conductive vias (also termed as thermal vias, thermal conductive pillars, or thermal pillars) on a semiconductor structure. The thermal vias, with material thermal conductivity greater than about 10 W/m·K, are embedded in the bonding structure that provides a quick dissipation path of heat from thermal hotspot regions into a substrate.

Abstract: A method of forming a semiconductor device includes depositing a target metal layer in an opening. Depositing the target metal layer comprises performing a plurality of deposition cycles. An initial deposition cycle of the plurality of deposition cycles comprises: flowing a first precursor in the opening, flowing a second precursor in the opening after flowing the first precursor, and flowing a reactant in the opening. The first precursor attaches to upper surfaces in the opening, and the second precursor attaches to remaining surfaces in the opening. The first precursor does not react with the second precursor, and the reactant reacts with the second precursor at a greater rate than the reactant reacts with the first precursor.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an interconnect structure disposed over a semiconductor substrate, contact pads disposed on the interconnect structure, a dielectric structure disposed on the interconnect structure and covering the contact pads, bonding connectors covered by the dielectric structure and landing on the contact pads, and a dummy feature covered by the dielectric structure and laterally interposed between adjacent two of the bonding connectors. Top surfaces of the bonding connectors are substantially coplanar with a top surface of the dielectric structure, and the bonding connectors are electrically coupled to the interconnect structure through the contact pads.

Abstract: A plating apparatus includes a workpiece holder, a plating bath, and a clamp ring. The plating bath is underneath the workpiece holder. The clamp ring is connected to the workpiece holder. The clamp ring includes channels communicating an inner surface of the clamp ring and an outer surface of the clamp ring.

Abstract: Method to implement heat dissipation multilayer and reduce thermal boundary resistance for high power consumption semiconductor devices is provided. The heat dissipation multilayer comprises a first crystalline layer that possesses a first phonon frequency range, a second crystalline layer that has a second phonon frequency range which does not overlap with the first phonon frequency range, and an amorphous layer located between the first and second crystalline layers. The amorphous layer has a third phonon frequency range that overlaps both the first and second phonon frequency ranges.

Abstract: Method to form low-contact-resistance contacts to source/drain features are provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, selectively depositing a first silicide layer on the surface of the p-type source/drain feature while the surface of the n-type source/drain feature is substantially free of the first silicide layer, depositing a metal layer on the first silicide layer and the surface of the n-type source/drain feature, and depositing a second silicide layer over the metal layer. The selectively depositing includes passivating the surface of the surface of the n-type source/drain features with a self-assembly layer, selectively depositing the first silicide layer on the surface of the p-type source/drain feature, and removing the self-assembly layer.

Abstract: Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a semiconductor substrate, a high-Kappa dielectric layer disposed on the semiconductor substrate, a first plurality of nanostructures disposed over the high-Kappa dielectric layer, a middle dielectric layer disposed over the first plurality of nanostructures, a second plurality of nanostructures over the middle dielectric layer, a first gate structure wrapping around the first plurality of nanostructures, a second gate structure wrapping around the second plurality of nanostructures. The high-Kappa dielectric layer includes metal nitride, metal oxide, silicon carbide, graphene, or diamond.

Abstract: A method includes putting a first package component into contact with a second package component. The first package component comprises a first dielectric layer including a first dielectric material, and the first dielectric material is a silicon-oxide-based dielectric material. The second package component includes a second dielectric layer including a second dielectric material different from the first dielectric material. The second dielectric material comprises silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof. An annealing process is performed to bond the first dielectric layer to the second dielectric layer.

Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

Abstract: A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed. A contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.

Abstract: Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

Abstract: A method of forming an IC structure includes bonding a first die to a first side of a substrate and bonding a second die to the first side of the substrate. The second die is adjacent to the first die and a gap is defined between the first and second dies. The method includes forming a first dielectric layer (DL) over the first and second dies and in the gap, forming a first opening in the first DL in the gap, forming a second DL over the first DL and in the first opening. The first DL includes a higher film stress in absolute value than the second DL.

Abstract: Semiconductor structures and processes of forming the same are provided. A semiconductor structure according to the present disclosure includes a first bottom source/drain feature and a second bottom source/drain feature disposed over a substrate, a plurality of bottom channel members extending between and in contact with the first bottom source/drain feature and the second bottom source/drain feature, a first bonding layer over the plurality of bottom channel members, a second bonding layer disposed directly on the first bonding layer, a first top source/drain feature disposed directly over the first bottom source/drain feature, a second top source/drain feature disposed directly over the second bottom source/drain feature, and a plurality of top channel members disposed over the second bonding layer and extending between and in contact with the first top source/drain feature and the second top source/drain feature.

Abstract: Methods of forming gate structures for stacked multi-gate devices are provided. A method according to the present disclosure includes forming a gate dielectric layer to wrap around a bottom channel member and a top channel member, depositing a dipole layer over the gate dielectric layer, forming a dummy layer such that the top channel member is disposed above the top surface of the dummy layer, removing the dipole layer around the top channel member, forming a self-assembled monolayer (SAM) on the top surface of the dummy layer, depositing a hard mask layer to wrap over the top channel member, removing the SAM and the dummy layer, performing a thermal drive-in process to drive a dipole dopant species from the dipole layer into the gate dielectric layer around the bottom channel member, removing the hard mask layer, and removing the dipole layer.

Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.