Abstract: Methods and devices that include forming a first epitaxial region and a second epitaxial region above the first epitaxial region. An opening may be formed extending from the first region to the second region. And a liner layer is deposited on a sidewall and a bottom of the opening. A plasma treatment is performed on the liner layer, which can form a conditioned or passivated region of the first epitaxial region that may be maintained during the growth of additional epitaxial material on the second epitaxial region.

Abstract: A method includes forming a device layer on a first surface of a first substrate, forming a first interconnect structure over the device layer, depositing a bonding layer over the first interconnect structure, forming a diamond layer over the bonding layer, performing a laser treatment on a top portion of the diamond layer by applying laser energy to the top portion of the diamond layer using a laser beam, and performing a thinning process on the diamond layer to remove the top portion of the diamond layer.

Abstract: In an embodiment, a method includes forming an opening in a dielectric layer; filling the opening with a conductive material; and performing a chemical mechanical polishing process on the conductive material and the dielectric layer, the chemical mechanical polishing process comprising a slurry, the slurry comprising: abrasives, the abrasives comprising titania-silica hybrid particles; and an oxidizer.

Abstract: A method includes performing a cleaning process on a first surface of a first wafer, and performing a surface activation process on the first surface. The surface activation process is selected from the group consisting of: a plasma surface activation process comprising generating a plasma from a process gas, wherein ions in the plasma are removed using a filter, and wherein a remaining uncharged part of the plasma is used to treat the first surface; a laser surface activation process using a laser beam; an acid surface activation process using an acid; and an alkali surface activation process using an alkali. After the surface activation process, a rinsing process is performed on the first surface. The first surface of the first wafer is bonded to a second surface of a second wafer.

Abstract: A semiconductor apparatus for pre-wetting a semiconductor workpiece includes a process chamber, a workpiece holder disposed within the process chamber to hold the semiconductor workpiece, a pre-wetting fluid tank disposed outside the process chamber and containing a pre-wetting fluid, and a conduit coupled to the pre-wetting fluid tank and extending into the process chamber. The conduit delivers the pre-wetting fluid from the pre-wetting fluid tank out through an outlet of the conduit to wet a major surface of the semiconductor workpiece, wherein the outlet of the conduit is positioned above the major surface of the semiconductor workpiece by a vertical distance.

Abstract: A method includes forming a lower semiconductor region, forming an upper semiconductor region overlapping the lower semiconductor region, forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region, respectively, forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric, etching back the lower gate electrode, forming a gate isolation layer on the lower gate electrode that has been etched back, and forming an upper gate electrode over the gate isolation layer. The upper gate electrode is on the upper gate dielectric.

Abstract: A method includes putting a first package component into contact with a second package component. The first package component comprises a first dielectric layer including a first dielectric material, and the first dielectric material is a silicon-oxide-based dielectric material. The second package component includes a second dielectric layer including a second dielectric material different from the first dielectric material. The second dielectric material comprises silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof. An annealing process is performed to bond the first dielectric layer to the second dielectric layer.

Abstract: High resolution 3D thermal imaging can be obtained by using enhanced non-destructive heat transducer designs. A thermal property measurement method includes providing a sample for thermal property measurement, and bonding a transducer layer on the sample through a temporary bonding layer. Thermal measurement processes are performed along the X-Y, X-Z and Y-Z planes of the sample, wherein the X-Y plane is parallel to a top surface of the sample, and the X-Z plane and Y-Z plane are perpendicular to the top surface of the sample. Each thermal measurement processes include heating a designated region of the sample covered with the transducer layer using a pump laser, and using a probe laser for generating a reflectance signal of the sample, and determining a thermal conductivity in the designated region of the sample from the reflectance signal. Furthermore, the transducer layer is removed along with the temporary bonding layer from the sample.

Abstract: A method includes forming a multi-layer stack including a plurality of semiconductor nanostructures. The multi-layer stack includes a semiconductor nanostructure, and a sacrificial semiconductor layer over the semiconductor nanostructure. The method further includes depositing a semiconductor layer over and contacting the semiconductor nanostructure, removing the sacrificial semiconductor layer, and forming a replacement gate stack encircling a combined region of the semiconductor nanostructure and the semiconductor layer.

Abstract: A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed, a contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.

Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Abstract: A manufacturing method of a semiconductor structure is provided. The method includes: forming contact pads on an interconnect structure over a semiconductor substrate; forming a dielectric material stack on the interconnect structure; forming holes and a recess in the dielectric material stack to form a dielectric structure, wherein the holes accessibly expose portions of the contact pads, and the recess is formed between adjacent two of the holes; and forming conductive materials in the holes and the recess to respectively form bonding connectors and a dummy feature. The bonding connectors land on the contact pads, and the dummy feature is isolated and substantially equidistant from adjacent two of the bonding connectors.

Abstract: Source/drain fabrication methods for stacked device structures are disclosed herein. An exemplary method for forming a source/drain stack may include a frontside process and a backside process. The frontside process may include forming a frontside source/drain trench, forming a dummy source/drain in the frontside source/drain trench, and forming an upper source/drain in the frontside source/drain trench over the dummy source/drain. The backside process may include exposing a backside of the dummy source/drain, removing (partially or completely) the dummy source/drain to form a backside source/drain trench, and forming a lower source/drain in the backside source/drain trench. The dummy source/drain may be formed of semiconductor material or dielectric material, and a portion of the dummy source/drain may remain between the upper source/drain and the lower source/drain.

Abstract: A plating apparatus includes a workpiece holder. a plating bath, and a clamp ring. The plating bath is underneath the workpiece holder. The clamp ring is connected to the workpiece holder. The clamp ring includes channels communicating an inner surface of the clamp ring and an outer surface of the clamp ring.

Abstract: Semiconductor structures and method of forming the same are provided. A method according to the present disclosure includes providing an intermediate structure that includes an opening, conformally depositing a metal liner over the opening, depositing a dummy fill material over the metal liner, recessing the dummy fill material such that a portion of the metal liner is exposed, removing the exposed portion of the metal liner, removing the recessed dummy fill material, and after the removing of the recessed dummy fill material, depositing a metal fill layer over the opening.

Abstract: The present disclosure provides an integrated circuit (IC) structure in accordance with some embodiments. The IC structure includes a circuit structure having semiconductor devices formed on a first substrate, an interconnect structure over the semiconductor devices; and a thermal dissipation structure formed on a second substrate. The second substrate is boned to the circuit structure such that the thermal dissipation structure is interposed between the first and second substrates. The thermal dissipation structure includes a diamond-like carbon (DLC) layer. The DLC layer includes a bottom portion having large grain sizes and a top portion having fine DLC grain sizes.

Abstract: A method includes forming a first de-bond structure over a first substrate, where forming the first de-bond structure includes depositing a first de-bond layer over the first substrate, depositing a first silicon layer over the first de-bond layer, depositing a second de-bond layer over the first silicon layer, and depositing a second silicon layer over the second de-bond layer, epitaxially growing a first multi-layer stack over the first de-bond structure, bonding the first multi-layer stack to a second multi-layer stack, and performing a first laser annealing process to ablate the first silicon layer and portions of the first de-bond layer and the second de-bond layer in order to de-bond the first substrate from the first multi-layer stack.

Abstract: The present disclosure relates to an integrated circuit (IC) structure. The IC structure includes a semiconductor device having a frontside and a backside opposite the frontside. A first interconnect structure disposed on the frontside of the semiconductor device. The first interconnect structure comprises a first dielectric structure having a plurality of inter-level dielectric (ILD) layers. A second dielectric structure disposed on the backside of the semiconductor device. The second dielectric structure comprises a first high thermal conductivity layer having a thermal conductivity greater than that of the ILD layers.

Abstract: A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.

Abstract: A method includes forming a bonding structure that contains thermal conductive vias (also termed as thermal vias, thermal conductive pillars, or thermal pillars) on a semiconductor structure. The thermal vias, with material thermal conductivity greater than about 10 W/m·K, are embedded in the bonding structure that provides a quick dissipation path of heat from thermal hotspot regions into a substrate.