Patents by Inventor Ku-Feng Yang

Ku-Feng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of making integrated circuits including conductive structures through substrates
    Patent number: 9773701
    Abstract: A method of forming an integrated circuit includes forming at least one opening through a first surface of a substrate. The method further includes forming at least one conductive structure in the at least one opening. The method further includes removing a portion of the substrate to form a processed substrate having the first surface and a second surface opposite the first surface and to expose a portion of the at least one conductive structure adjacent to the second surface. The at least one conductive structure continuously extending from the first surface through the processed substrate to the second surface of the processed substrate, at least one sidewall of the at least one conductive structure spaced from a sidewall of the at least one opening by an air gap.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Hung Liu, Ku-Feng Yang, Pei-Ching Kuo, Ming-Tsu Chung, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Interconnect Structure and Method of Forming Same
    Publication number: 20170271287
    Abstract: A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Dummy structure for chip-on-wafer-on-substrate
    Patent number: 9754831
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Through substrate vias with improved connections
    Patent number: 9704783
    Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ku-Feng Yang
  • Semiconductor Device and Method
    Publication number: 20170194286
    Abstract: A semiconductor device and method are provided which utilizes a single mask to form openings for both a through substrate via as well as for a through dielectric via. In an embodiment a contact etch stop layer is deposited over and between a first semiconductor device and a second semiconductor device. A dielectric material is deposited over the contact etch stop layer between the first semiconductor device and the second semiconductor device. The different materials of the contact etch stop layer and the dielectric material is utilized such that a single mask may be used to form a through substrate via through the first semiconductor device and also to form a through dielectric via through the dielectric material.
    Type: Application
    Filed: March 20, 2017
    Publication date: July 6, 2017
    Inventors: Cheng-Chun Tsai, Hung-Pin Chang, Ku-Feng Yang, Yi-Hsiu Chen, Wen-Chih Chiou
  • Interconnect structure and method of forming same
    Patent number: 9679859
    Abstract: An apparatus comprises a dielectric layer formed on a first side of a substrate, a first side interconnect structure comprising a first metal line and a pad formed in the dielectric layer, wherein the pad comprises a bottom portion formed of a first conductive metal and an upper portion formed of a second conductive metal, and wherein sidewalls of the upper portion are surrounded by the bottom portion and a top surface of the pad is coplanar with a top surface of the first metal line and a passivation layer formed over the dielectric layer.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • TSV formation
    Patent number: 9633929
    Abstract: A device includes a substrate having a front side and a backside, the backside being opposite the front side. An isolation layer is disposed on the front side of the substrate, wherein first portions of isolation layer and the substrate are in physical contact. A through substrate via (TSV) extends from the front side to the backside of the substrate. An oxide liner is on a sidewall of the TSV. The oxide liner extends between second portions of the substrate and the isolation layer. A dielectric layer having a metal pad is disposed over the isolation layer on the front side of the substrate. The metal pad and the TSV are formed of a same material.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Yang, Shin-Puu Jeng, Wen-Chih Chiou
  • Device with Through-Substrate Via Structure and Method for Forming the Same
    Publication number: 20170084489
    Abstract: A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventors: Yung-Chi Lin, Yen-Hung Chen, Yin-Hua Chen, Ebin Liao, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Semiconductor device and method
    Patent number: 9601410
    Abstract: A semiconductor device and method are provided which utilizes a single mask to form openings for both a through substrate via as well as for a through dielectric via. In an embodiment a contact etch stop layer is deposited over and between a first semiconductor device and a second semiconductor device. A dielectric material is deposited over the contact etch stop layer between the first semiconductor device and the second semiconductor device. The different materials of the contact etch stop layer and the dielectric material is utilized such that a single mask may be used to form a through substrate via through the first semiconductor device and also to form a through dielectric via through the dielectric material.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chun Tsai, Hung-Pin Chang, Ku-Feng Yang, Yi-Hsiu Chen, Wen-Chih Chiou
  • THREE DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20170062392
    Abstract: Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Kuang-Wei Cheng, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Three dimensional integrated circuit structure and manufacturing method of the same
    Patent number: 9583465
    Abstract: Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuang-Wei Cheng, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via and Method of Forming the Same
    Publication number: 20170011988
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 12, 2017
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Dummy Structure for Chip-on-Wafer-on-Substrate
    Publication number: 20160358818
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Device with capped through-substrate via structure
    Patent number: 9514986
    Abstract: A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Yen-Hung Chen, Yin-Hua Chen, Ebin Liao, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Semiconductor device having backside interconnect structure through substrate via and method of forming the same
    Patent number: 9449898
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Dummy structure for chip-on-wafer-on-substrate
    Patent number: 9425126
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Semiconductor Device and Method
    Publication number: 20160240439
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 18, 2016
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Through-substrate via formation with improved topography control
    Patent number: 9418933
    Abstract: A device include a substrate and an interconnect structure over the substrate. The interconnect structure comprising an inter-layer dielectric (ILD) and a first inter-metal dielectric (IMD) formed over the ILD. A through-substrate via (TSV) is formed at the IMD extending a first depth through the interconnect structure into the substrate. A metallic pad is formed at the IMD adjoining the TSV and extending a second depth into the interconnect structure, wherein the second depth is less than the first depth. Connections to the TSV are made through the metallic pad.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • TSV Formation Processes Using TSV-Last Approach
    Publication number: 20160225668
    Abstract: A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.
    Type: Application
    Filed: April 8, 2016
    Publication date: August 4, 2016
    Inventors: Jing-Cheng Lin, Yung-Chi Lin, Ku-Feng Yang
  • Semiconductor Device and Method
    Publication number: 20160197029
    Abstract: A semiconductor device and method are provided which utilizes a single mask to form openings for both a through substrate via as well as for a through dielectric via. In an embodiment a contact etch stop layer is deposited over and between a first semiconductor device and a second semiconductor device. A dielectric material is deposited over the contact etch stop layer between the first semiconductor device and the second semiconductor device. The different materials of the contact etch stop layer and the dielectric material is utilized such that a single mask may be used to form a through substrate via through the first semiconductor device and also to form a through dielectric via through the dielectric material.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 7, 2016
    Inventors: Cheng-Chun Tsai, Hung-Pin Chang, Ku-Feng Yang, Yi-Hsiu Chen, Wen-Chih Chiou