Abstract: A winding member, including a winding core for an electrode assembly, winding a positive electrode plate, a negative electrode plate, and a first separator, the winding core including a pair of clamps extending along a longitudinal direction of the winding core a base portion coupled to a first and second end of each of the clamps the clamps being spaced apart from each other vertically around an insertion groove, the clamps including a first clamp and a second clamp extending along the longitudinal direction the first clamp including a pair of protrusions protruding in the direction of the second clamp on an inner surface of the first clamp, and at least one of the pair of protrusions fixing a winding-front end of the first separator inserted into the insertion groove to an inner surface of the second clamp.

Abstract: The present disclosure proposes an adaptive non-speculative DFE with an extended time constraint for a PAM-4 receiver and a method for operating the same. An adaptive non-speculative DFE with an extended time constraint for a PAM-4 receiver according to the present disclosure comprises a Continuous-Time Linear Equalizer (CTLE) to boost high-frequency components of an input signal, a Track and Hold (T&H) circuit to track and hold an output of the CTLE, and a sampler, wherein the sampler includes a Decision Feedback Equalization (DFE) sampler to equalize an output of the T&H circuit and sample an output of the T&H circuit in a DFE sampling clock phase; and a DATA sampler to sample a signal equalized by the DFE sampler in a DATA sampling clock phase, wherein the DFE sampling clock phase differs from the DATA sampling clock phase.

Abstract: A method using a UWB for precisely positioning in an environment without a positioning infrastructure is provided. The method, when positioning objects of swarm objects in a free space, etc., calculates an object position of each object through cooperation with objects existing surrounding. In this state, positioning is simply performed without a specific anchor by defining objects as anchors in a UWB in accordance with an embodiment. In particular, cooperative positioning is quickly performed by reducing position errors of objects in accordance with pull-push relationships based on UWB TWR. Therefore, when a specific mission is performed in an environment in which a positioning infrastructure does not exist or is lost, such as a flight space, positioning is performed in the UWB-based cooperative positioning method described above, whereby precise positioning suitable for these environments is provided.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a gate stack including a plurality of gate patterns and a plurality of interlayer insulating layers alternately stacked with each other in a cell region, a source line disposed on the gate stack, and a channel plug passing through the gate stack and the source line in a vertical direction. The channel plug includes a backgate, a backgate insulating layer surrounding a sidewall of the backgate, a channel layer surrounding the sidewall of the backgate, and a memory layer surrounding a sidewall of the channel layer. The backgate insulating layer extends between the backgate and the source line.

Abstract: Provided herein may be a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a gate stacked structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked, a vertical structure extending into the gate stacked structure, a floating gate disposed between the vertical structure and the plurality of conductive layers, and a dielectric pattern disposed between the floating gate and the plurality of conductive layers. The floating gate may include a first portion that is adjacent to the vertical structure and a second portion that is adjacent to the dielectric pattern, and the dielectric pattern may contact an upper surface, a lower surface, and a sidewall of the second portion.

Abstract: A three dimensional semiconductor device is disclosed. The tree dimensional semiconductor device includes a word line stack over a substrate and a channel pillar structure passing through the word line stack in a vertical direction perpendicular to a top surface of the substrate. The channel pillar structure includes a channel structure. The channel structure includes a blocking layer, a trap layer, a tunneling layer, a channel layer, a filling layer, and a back gate electrode. The channel structure has a pillar shape.

Abstract: Provided herein are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stacked body including a plurality of interlayer insulating layers and a plurality of conductive layers that are alternately stacked, wherein a top-most conductive layer, among the plurality of conductive layers, corresponds to a backgate line and the rest of the plurality of conductive layers correspond to word lines, and a vertical channel structure passing through the gate stacked body. A first part of the vertical channel structure passing through the plurality of interlayer insulating layers and the plurality of conductive layers corresponding to the word lines has a circular structure in a plan view, and a second part of the vertical channel structure passing through the conductive layer corresponding to the backgate line has a pair of semicircular structures that are separated from each other in a plan view.

Abstract: A semiconductor device includes a stack structure including conductive patterns spaced apart from each other, a channel structure penetrating the stack structure, and a slit insulating layer penetrating the stack structure. Air gaps are defined between the conductive patterns. The slit insulating layer includes a first interposition part covering a sidewall of one of the conductive patterns and a second interposition part covering one of the air gaps from the side. A smallest width of the second interposition part is smaller than a smallest width of the first interposition part.

Abstract: An apparatus for manufacturing a display device, comprising a stage, a first electric-field-applying module on a first side of the stage, and including first probe pins, a first light-irradiating module above the stage, and configured to irradiate light to the stage, a first light emission driver configured to transmit a first emission driving signal to the first light-irradiating module, and a signal output unit configured to output a first emission timing signal for setting light irradiation timing of the first light-irradiating module to the first light emission driver, to output a first alignment signal to any one of the first probe pins, and to output a second alignment signal to another one of the first probe pins, wherein the first emission timing signal and the second alignment signal are alternating current (AC) signals, and wherein periods of the first emission timing signal and the second alignment signal are the same.

Abstract: Provided herein may be a resistive memory device and a method of operating the resistive memory device. The resistive memory device may include strings coupled between one or more source lines and one or more bit lines, each string including a set of one or more resistive memory cells, one or more word lines respectively coupled to the set of one or more resistive memory cells; and a voltage generator configured to control a level of a turn-on voltage to be applied to one or more unselected word lines among the one or more word lines depending on a program target state of a subset of resistive memory cells including one or more resistive memory cells selected from among the set of one or more resistive memory cells.

Abstract: The present disclosure relates to a sub-nanometric particles-metal organic framework complex including a multi-shell hollow metal organic framework (MOF) and sub-nanometric particles (SNPs), and a method of preparing the same.

Abstract: The present technology relates to a resistive memory device and a method of manufacturing the same. The resistive memory device includes a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked, a hole passing through the stack structure in a vertical direction, a gate insulating layer, a channel layer, and a variable resistance layer sequentially formed along a sidewall of the hole, and a high dielectric layer formed between the channel layer and the gate insulating layer, the high dielectric layer being adjacent to the plurality of interlayer insulating layers.

Abstract: A semiconductor device includes a stack structure including conductive patterns spaced apart from each other, a channel structure penetrating the stack structure, and a slit insulating layer penetrating the stack structure. Air gaps are defined between the conductive patterns. The slit insulating layer includes a first interposition part covering a sidewall of one of the conductive patterns and a second interposition part covering one of the air gaps from the side. A smallest width of the second interposition part is smaller than a smallest width of the first interposition part.

Abstract: Provided herein may be a resistive memory device and a method of operating the resistive memory device. The resistive memory device may include strings coupled between one or more source lines and one or more bit lines, each string including a set of one or more resistive memory cells, one or more word lines respectively coupled to the set of one or more resistive memory cells; and a voltage generator configured to control a level of a turn-on voltage to be applied to one or more unselected word lines among the one or more word lines depending on a program target state of a subset of resistive memory cells including one or more resistive memory cells selected from among the set of one or more resistive memory cells.

Abstract: A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; air gaps located between the memory patterns; and a sealing layer including first parts respectively including the air gaps and a second part extending between the memory patterns.

Abstract: A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; a blocking layer including first parts located between the conductive layers and the memory patterns and second parts extending between the memory patterns; and air gaps respectively located between the blocking layer and the insulating layers.

Abstract: A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; a blocking layer including first parts located between the memory patterns and the conductive layers, and second parts extending between the memory patterns and protruding toward the insulating layers to the inside of the gate structure; and air gaps including a first region located in the second parts and a second region located between the memory patterns.

Abstract: The present disclosure relates to a triphasic metal oxide composite including a nanosheet and a core-shell structure, a photocatalyst including the same, and a method of preparing the same.

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns, wherein a sidewall of each of the conductive layers protrudes farther towards the channel structure than a sidewall of the hard mask pattern, and wherein the insulating patterns protrude farther towards the channel structure than the sidewall of each of the conductive layers.

Abstract: Provided is a refrigerator. The refrigerator includes a main body provided to form a storage chamber, a storage container configured to be inserted into or withdrawn from the storage chamber, and having a storage space, a divider configured to be movable with respect to the storage container to divide the storage space, a support shaft arranged in the storage container and configured to guide movement of the divider, and a guide device configured to movably support the divider, and having a plurality of ball bearings arranged to roll with respect to the support shaft.