Patents by Inventor Ku-Youl Jung

Ku-Youl Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230180620
    Abstract: A method for fabricating a semiconductor device may include: forming a first magnetic layer over a substrate; forming a tunnel barrier layer over the first magnetic layer by repeatedly performing a unit process of forming a material layer and performing a rapid thermal annealing (RTA) process on the material layer; and forming a second magnetic layer over the tunnel barrier layer.
    Type: Application
    Filed: October 19, 2022
    Publication date: June 8, 2023
    Inventors: Ku Youl JUNG, Jung Hyeok KWAK, Jin Won JUNG, Young Min EEH
  • Publication number: 20230026414
    Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.
    Type: Application
    Filed: October 3, 2022
    Publication date: January 26, 2023
    Applicants: KIOXIA CORPORATION, SK HYNIX INC.
    Inventors: Taiga ISODA, Eiji KITAGAWA, Young Min Min EEH, Tadaaki OIKAWA, Kazuya SAWADA, Kenichi YOSHINO, Jong Koo LIM, Ku Youl JUNG, Guk Cheon Cheon KIM
  • Patent number: 11495740
    Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 8, 2022
    Assignees: KIOXIA CORPORATION, SK HYNIX INC.
    Inventors: Taiga Isoda, Eiji Kitagawa, Young Min Eeh, Tadaaki Oikawa, Kazuya Sawada, Kenichi Yoshino, Jong Koo Lim, Ku Youl Jung, Guk Cheon Kim
  • Publication number: 20220302372
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, a non-magnetic layer provided between the first magnetic layer and the second magnetic layer, and an oxide layer provided adjacent to the first magnetic layer, the first magnetic layer being provided between the non-magnetic layer and the oxide layer, and the oxide layer containing a rare earth element, boron (B), and oxygen (O).
    Type: Application
    Filed: September 10, 2021
    Publication date: September 22, 2022
    Applicants: Kioxia Corporation, SK hynix Inc.
    Inventors: Tadaaki OIKAWA, Youngmin EEH, Eiji KITAGAWA, Kazuya SAWADA, Taiga ISODA, Ku Youl JUNG, Jin Won JUNG
  • Publication number: 20220302205
    Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a fixed magnetization direction, a second magnetic layer having a variable magnetization direction, a non-magnetic layer provided between the first magnetic layer and the second magnetic layer, a molybdenum (Mo) layer provided on an opposite side of the non-magnetic layer with respect to the second magnetic layer, and an oxide layer provided between the second magnetic layer and the molybdenum (Mo) layer and containing a predetermined element selected from a rare earth element, silicon (Si) and aluminum (Al).
    Type: Application
    Filed: September 10, 2021
    Publication date: September 22, 2022
    Applicants: Kioxia Corporation, SK hynix Inc.
    Inventors: Tadaaki OIKAWA, Youngmin EEH, Eiji KITAGAWA, Taiga ISODA, Ku Youl JUNG, Jin Won JUNG
  • Patent number: 10978637
    Abstract: A method for fabricating an electronic device including a semiconductor memory may include forming a buffer layer over a substrate, the buffer layer operable to aide in crystal growth of an under layer; forming the under layer over the buffer layer, the under layer operable to aide in crystal growth of a free layer; and forming a Magnetic Tunnel Junction (MTJ) structure including the free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer over the under layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Ku-Youl Jung, Guk-Cheon Kim, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
  • Publication number: 20210074911
    Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.
    Type: Application
    Filed: March 10, 2020
    Publication date: March 11, 2021
    Applicants: KIOXIA CORPORATION, SK HYNIX INC.
    Inventors: Taiga ISODA, Eiji KITAGAWA, Young Min EEH, Tadaaki OIKAWA, Kazuya SAWADA, Kenichi YOSHINO, Jong Koo LIM, Ku Youl JUNG, Guk Cheon KIM
  • Patent number: 10923168
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
  • Patent number: 10685692
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer including a CoFeBAl alloy and having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the CoFeBAl alloy may have an Al content less than 10 at %.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: June 16, 2020
    Assignee: SK hynix Inc.
    Inventors: Jong-Koo Lim, Yang-Kon Kim, Ku-Youl Jung, Guk-Cheon Kim, Jeong-Myeong Kim
  • Publication number: 20200185017
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
  • Patent number: 10586917
    Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 10, 2020
    Assignees: SK hynix Inc., TOSHIBA MEMORY CORPORATION
    Inventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine
  • Patent number: 10566041
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
  • Patent number: 10516099
    Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes a magnetic tunnel junction (MTJ) structure including: a free layer having a changeable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer sandwiched between the free layer and the pinned layer, wherein the free layer includes a CoFeAlB alloy.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: December 24, 2019
    Assignee: SK hynix Inc.
    Inventors: Seung-Mo Noh, Yang-Kon Kim, Ku-Youl Jung, Bo-Mi Lee
  • Patent number: 10395708
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer may include: a first sublayer having a damping constant of 0.1 or less; a second sublayer having a perpendicular magnetic anisotropy energy density ranging from 1.0×104 to 1.0×108 erg/cm3; and an insertion layer interposed between the first sublayer and the second sublayer.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventors: Ku-Youl Jung, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
  • Patent number: 10305028
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include an MTJ (Magnetic Tunnel Junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; an under layer disposed under the MTJ structure; and a perpendicular magnetic anisotropy increasing layer disposed below the under layer and including a material having a different crystal structure from the under layer.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Yang-Kon Kim, Ku-Youl Jung, Jong-Koo Lim, Jae-Hyoung Lee
  • Publication number: 20190109280
    Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 11, 2019
    Inventors: Jong-Koo LIM, Won-Joon CHOI, Guk-Cheon KIM, Yang-Kon KIM, Ku-Youl JUNG, Toshihiko NAGASE, Youngmin EEH, Daisuke WATANABE, Kazuya SAWADA, Makoto NAGAMINE
  • Publication number: 20190074041
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer may include: a first sublayer having a damping constant of 0.1 or less; a second sublayer having a perpendicular magnetic anisotropy energy density ranging from 1.0×104 to 1.0×108 erg/cm3; and an insertion layer interposed between the first sublayer and the second sublayer.
    Type: Application
    Filed: August 6, 2018
    Publication date: March 7, 2019
    Inventors: Ku-Youl Jung, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
  • Publication number: 20190074042
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.
    Type: Application
    Filed: August 6, 2018
    Publication date: March 7, 2019
    Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
  • Patent number: 10203380
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 12, 2019
    Assignees: SK Hynix Inc., Toshiba Memory Corporation
    Inventors: Ku-Youl Jung, Guk-Cheon Kim, Toshihiko Nagase, Daisuke Watanabe, Won-Joon Choi, Youngmin Eeh, Kazuya Sawada
  • Patent number: 10170691
    Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: January 1, 2019
    Assignees: SK Hynix Inc., TOSHIBA MEMORY CORPORATION
    Inventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine