Patents by Inventor Ku-Youl Jung
Ku-Youl Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230180620Abstract: A method for fabricating a semiconductor device may include: forming a first magnetic layer over a substrate; forming a tunnel barrier layer over the first magnetic layer by repeatedly performing a unit process of forming a material layer and performing a rapid thermal annealing (RTA) process on the material layer; and forming a second magnetic layer over the tunnel barrier layer.Type: ApplicationFiled: October 19, 2022Publication date: June 8, 2023Inventors: Ku Youl JUNG, Jung Hyeok KWAK, Jin Won JUNG, Young Min EEH
-
Publication number: 20230026414Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.Type: ApplicationFiled: October 3, 2022Publication date: January 26, 2023Applicants: KIOXIA CORPORATION, SK HYNIX INC.Inventors: Taiga ISODA, Eiji KITAGAWA, Young Min Min EEH, Tadaaki OIKAWA, Kazuya SAWADA, Kenichi YOSHINO, Jong Koo LIM, Ku Youl JUNG, Guk Cheon Cheon KIM
-
Patent number: 11495740Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.Type: GrantFiled: March 10, 2020Date of Patent: November 8, 2022Assignees: KIOXIA CORPORATION, SK HYNIX INC.Inventors: Taiga Isoda, Eiji Kitagawa, Young Min Eeh, Tadaaki Oikawa, Kazuya Sawada, Kenichi Yoshino, Jong Koo Lim, Ku Youl Jung, Guk Cheon Kim
-
Publication number: 20220302372Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, a non-magnetic layer provided between the first magnetic layer and the second magnetic layer, and an oxide layer provided adjacent to the first magnetic layer, the first magnetic layer being provided between the non-magnetic layer and the oxide layer, and the oxide layer containing a rare earth element, boron (B), and oxygen (O).Type: ApplicationFiled: September 10, 2021Publication date: September 22, 2022Applicants: Kioxia Corporation, SK hynix Inc.Inventors: Tadaaki OIKAWA, Youngmin EEH, Eiji KITAGAWA, Kazuya SAWADA, Taiga ISODA, Ku Youl JUNG, Jin Won JUNG
-
Publication number: 20220302205Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a fixed magnetization direction, a second magnetic layer having a variable magnetization direction, a non-magnetic layer provided between the first magnetic layer and the second magnetic layer, a molybdenum (Mo) layer provided on an opposite side of the non-magnetic layer with respect to the second magnetic layer, and an oxide layer provided between the second magnetic layer and the molybdenum (Mo) layer and containing a predetermined element selected from a rare earth element, silicon (Si) and aluminum (Al).Type: ApplicationFiled: September 10, 2021Publication date: September 22, 2022Applicants: Kioxia Corporation, SK hynix Inc.Inventors: Tadaaki OIKAWA, Youngmin EEH, Eiji KITAGAWA, Taiga ISODA, Ku Youl JUNG, Jin Won JUNG
-
Patent number: 10978637Abstract: A method for fabricating an electronic device including a semiconductor memory may include forming a buffer layer over a substrate, the buffer layer operable to aide in crystal growth of an under layer; forming the under layer over the buffer layer, the under layer operable to aide in crystal growth of a free layer; and forming a Magnetic Tunnel Junction (MTJ) structure including the free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer over the under layer.Type: GrantFiled: February 2, 2018Date of Patent: April 13, 2021Assignee: SK hynix Inc.Inventors: Ku-Youl Jung, Guk-Cheon Kim, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
-
Publication number: 20210074911Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.Type: ApplicationFiled: March 10, 2020Publication date: March 11, 2021Applicants: KIOXIA CORPORATION, SK HYNIX INC.Inventors: Taiga ISODA, Eiji KITAGAWA, Young Min EEH, Tadaaki OIKAWA, Kazuya SAWADA, Kenichi YOSHINO, Jong Koo LIM, Ku Youl JUNG, Guk Cheon KIM
-
Patent number: 10923168Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.Type: GrantFiled: February 18, 2020Date of Patent: February 16, 2021Assignee: SK hynix Inc.Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
-
Patent number: 10685692Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer including a CoFeBAl alloy and having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the CoFeBAl alloy may have an Al content less than 10 at %.Type: GrantFiled: January 22, 2018Date of Patent: June 16, 2020Assignee: SK hynix Inc.Inventors: Jong-Koo Lim, Yang-Kon Kim, Ku-Youl Jung, Guk-Cheon Kim, Jeong-Myeong Kim
-
Publication number: 20200185017Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
-
Patent number: 10586917Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.Type: GrantFiled: November 28, 2018Date of Patent: March 10, 2020Assignees: SK hynix Inc., TOSHIBA MEMORY CORPORATIONInventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine
-
Patent number: 10566041Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.Type: GrantFiled: August 6, 2018Date of Patent: February 18, 2020Assignee: SK hynix Inc.Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
-
Patent number: 10516099Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes a magnetic tunnel junction (MTJ) structure including: a free layer having a changeable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer sandwiched between the free layer and the pinned layer, wherein the free layer includes a CoFeAlB alloy.Type: GrantFiled: May 25, 2016Date of Patent: December 24, 2019Assignee: SK hynix Inc.Inventors: Seung-Mo Noh, Yang-Kon Kim, Ku-Youl Jung, Bo-Mi Lee
-
Patent number: 10395708Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer may include: a first sublayer having a damping constant of 0.1 or less; a second sublayer having a perpendicular magnetic anisotropy energy density ranging from 1.0×104 to 1.0×108 erg/cm3; and an insertion layer interposed between the first sublayer and the second sublayer.Type: GrantFiled: August 6, 2018Date of Patent: August 27, 2019Assignee: SK hynix Inc.Inventors: Ku-Youl Jung, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
-
Patent number: 10305028Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include an MTJ (Magnetic Tunnel Junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; an under layer disposed under the MTJ structure; and a perpendicular magnetic anisotropy increasing layer disposed below the under layer and including a material having a different crystal structure from the under layer.Type: GrantFiled: March 2, 2018Date of Patent: May 28, 2019Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Ku-Youl Jung, Jong-Koo Lim, Jae-Hyoung Lee
-
Publication number: 20190109280Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.Type: ApplicationFiled: November 28, 2018Publication date: April 11, 2019Inventors: Jong-Koo LIM, Won-Joon CHOI, Guk-Cheon KIM, Yang-Kon KIM, Ku-Youl JUNG, Toshihiko NAGASE, Youngmin EEH, Daisuke WATANABE, Kazuya SAWADA, Makoto NAGAMINE
-
Publication number: 20190074041Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer may include: a first sublayer having a damping constant of 0.1 or less; a second sublayer having a perpendicular magnetic anisotropy energy density ranging from 1.0×104 to 1.0×108 erg/cm3; and an insertion layer interposed between the first sublayer and the second sublayer.Type: ApplicationFiled: August 6, 2018Publication date: March 7, 2019Inventors: Ku-Youl Jung, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
-
Publication number: 20190074042Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.Type: ApplicationFiled: August 6, 2018Publication date: March 7, 2019Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
-
Patent number: 10203380Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.Type: GrantFiled: December 14, 2017Date of Patent: February 12, 2019Assignees: SK Hynix Inc., Toshiba Memory CorporationInventors: Ku-Youl Jung, Guk-Cheon Kim, Toshihiko Nagase, Daisuke Watanabe, Won-Joon Choi, Youngmin Eeh, Kazuya Sawada
-
Patent number: 10170691Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.Type: GrantFiled: June 20, 2016Date of Patent: January 1, 2019Assignees: SK Hynix Inc., TOSHIBA MEMORY CORPORATIONInventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine