Patents by Inventor Ku-Youl Jung
Ku-Youl Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10153423Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.Type: GrantFiled: December 15, 2017Date of Patent: December 11, 2018Assignees: SK Hynix Inc., Toshiba Memory CorporationInventors: Yang-Kon Kim, Guk-Cheon Kim, Jae-Hyoung Lee, Jong-Koo Lim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh
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Publication number: 20180323368Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include an MTJ (Magnetic Tunnel Junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; an under layer disposed under the MTJ structure; and a perpendicular magnetic anisotropy increasing layer disposed below the under layer and including a material having a different crystal structure from the under layer.Type: ApplicationFiled: March 2, 2018Publication date: November 8, 2018Inventors: Yang-Kon Kim, Ku-Youl Jung, Jong-Koo Lim, Jae-Hyoung Lee
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Publication number: 20180284199Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer between the free layer and the pinned layer, wherein the free layer may include a first magnetic layer; a second magnetic layer having a smaller perpendicular magnetic anisotropy energy density than the first magnetic layer; and a spacer interposed between the first magnetic layer and the second magnetic layer.Type: ApplicationFiled: December 14, 2017Publication date: October 4, 2018Inventors: Ku-Youl JUNG, Guk-Cheon KIM, Toshihiko NAGASE, Daisuke WATANABE, Won-Joon CHOI, Youngmin EEH, Kazuya SAWADA
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Publication number: 20180277745Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive element, the magnetoresistive element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The first magnetic layer includes first and second sub-magnetic layers each containing at least iron (Fe) and boron (B), and a concentration of boron (B) contained in the first sub-magnetic layer is different from a concentration of boron (B) contained in the second sub-magnetic layer.Type: ApplicationFiled: September 12, 2017Publication date: September 27, 2018Applicants: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.Inventors: Tadaaki OIKAWA, Toshihiko NAGASE, Youngmin EEH, Daisuke WATANABE, Kazuya SAWADA, Kenichi YOSHINO, Hiroyuki OHTORI, Yang Kon KIM, Ku Youl JUNG, Jong Koo LIM, Jae Hyoung LEE, Soo Man SEO, Sung Woong CHUNG, Tae Young LEE
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Patent number: 10062424Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.Type: GrantFiled: July 17, 2017Date of Patent: August 28, 2018Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Guk-Cheon Kim, Jeong-Myeong Kim, Jong-Koo Lim, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20180240973Abstract: A method for fabricating an electronic device including a semiconductor memory may include forming a buffer layer over a substrate, the buffer layer operable to aide in crystal growth of an under layer; forming the under layer over the buffer layer, the under layer operable to aide in crystal growth of a free layer; and forming a Magnetic Tunnel Junction (MTJ) structure including the free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer over the under layer.Type: ApplicationFiled: February 2, 2018Publication date: August 23, 2018Inventors: Ku-Youl Jung, Guk-Cheon Kim, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
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Publication number: 20180233187Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer including a CoFeBAl alloy and having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the CoFeBAl alloy may have an Al content less than 10 at %.Type: ApplicationFiled: January 22, 2018Publication date: August 16, 2018Inventors: Jong-Koo Lim, Yang-Kon Kim, Ku-Youl Jung, Guk-Cheon Kim, Jeong-Myeong Kim
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Patent number: 10042559Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an Fe-rich first layer; a Co-rich second layer formed over the first layer; and a metal layer formed over the second layer.Type: GrantFiled: January 30, 2017Date of Patent: August 7, 2018Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Guk-Cheon Kim, Ku-Youl Jung, Jong-Koo Lim, Won-Joon Choi
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Publication number: 20180211994Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory may include an MTJ (Magnetic Tunnel Junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer formed under the MTJ structure, wherein the under layer may include metals and oxides of the metals.Type: ApplicationFiled: November 2, 2017Publication date: July 26, 2018Inventors: Guk-Cheon Kim, Ku-Youl Jung, Yang-Kon Kim, Jae-Hyoung Lee, Jong-Koo Lim
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Publication number: 20180198060Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.Type: ApplicationFiled: December 15, 2017Publication date: July 12, 2018Inventors: Yang-Kon KIM, Guk-Cheon KIM, Jae-Hyoung LEE, Jong-Koo LIM, Ku-Youl JUNG, Toshihiko NAGASE, Youngmin EEH
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Patent number: 10002903Abstract: Implementations of the disclosed technology provide an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a magnetic tunnel junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer sandwiched between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer includes a first under layer including a silicon-based alloy, and a second under layer located on the first under layer and including a metal.Type: GrantFiled: March 18, 2016Date of Patent: June 19, 2018Assignee: SK hynix Inc.Inventors: Jong-Koo Lim, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Won-Joon Choi
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Patent number: 9841915Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure comprising a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer may include: a first under layer including a silicon-based alloy; a second under layer including a metal; and a blocking layer interposed between the first under layer and the second under layer and including an amorphous material.Type: GrantFiled: April 21, 2017Date of Patent: December 12, 2017Assignee: SK hynix Inc.Inventors: Jong-Koo Lim, Guk-Cheon Kim, Yang-Kon Kim, Seung-Mo Noh, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20170329518Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an Fe-rich first layer; a Co-rich second layer formed over the first layer; and a metal layer formed over the second layer.Type: ApplicationFiled: January 30, 2017Publication date: November 16, 2017Inventors: Yang-Kon Kim, Guk-Cheon Kim, Ku-Youl Jung, Jong-Koo Lim, Won-Joon Choi
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Publication number: 20170316814Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Yang-Kon Kim, Guk-Cheon Kim, Jeong-Myeong Kim, Jong-Koo Lim, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20170222133Abstract: Provided are electronic device including a variable resistance element and a method for fabricating an electronic device including a variable resistance element. The electronic device including a variable resistance element includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include cooling the substrate, before forming the magnetic correction layer such that the magnetic correction layer is formed over the cooled substrate.Type: ApplicationFiled: June 20, 2016Publication date: August 3, 2017Inventors: Jong-Koo LIM, Won-Joon CHOI, Guk-Cheon KIM, Yang-Kon KIM, Ku-Youl JUNG, Toshihiko NAGASE, Youngmin EEH, Daisuke WATANABE, Kazuya SAWADA, Makoto NAGAMINE
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Patent number: 9711202Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.Type: GrantFiled: March 17, 2016Date of Patent: July 18, 2017Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Guk-Cheon Kim, Jeong-Myeong Kim, Jong-Koo Lim, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20170154662Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.Type: ApplicationFiled: March 17, 2016Publication date: June 1, 2017Inventors: Yang-Kon Kim, Guk-Cheon Kim, Jeong-Myeong Kim, Jong-Koo Lim, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20170117457Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes a magnetic tunnel junction (MTJ) structure including: a free layer having a changeable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer sandwiched between the free layer and the pinned layer, wherein the free layer includes a CoFeAlB alloy.Type: ApplicationFiled: May 25, 2016Publication date: April 27, 2017Inventors: Seung-Mo Noh, Yang-Kon Kim, Ku-Youl Jung, Bo-Mi Lee
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Publication number: 20170084667Abstract: Implementations of the disclosed technology provide an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a magnetic tunnel junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer sandwiched between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer includes a first under layer including a silicon-based alloy, and a second under layer located on the first under layer and including a metal.Type: ApplicationFiled: March 18, 2016Publication date: March 23, 2017Inventors: Jong-Koo Lim, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Won-Joon Choi
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Patent number: 9532636Abstract: Provided is a cosmetic container having an airtight refill case that hermetically keeps a cosmetic such as a moisture-containing compact powder, a moisture-containing cream, and an eye shadow. More particularly, it relates to a cosmetic container having an airtight refill case 20 that is more hermetically sealed in a double airtight structure by coupling a lower main body 21 and an upper lid 25 of the refill case 20 with a butterfly hinge and by fitting an assembly groove part 22 having ring-shaped assembly protrusions 23 to an assembly protrusion part having ring-shaped assembly grooves 27 without a specific packing, in which the upper lid of the refill case is pressed by pressing protrusions 30 on the upper lid, when an outer container lid is closed.Type: GrantFiled: March 25, 2014Date of Patent: January 3, 2017Inventor: Ku Youl Jung