Patents by Inventor Kuan Cheng

Kuan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140294
    Abstract: A memory circuit includes a control circuit configured to receive a clock signal including a clock cycle and output control signals based on the clock signal, an input circuit arrangement configured to, responsive to the control signals, pass a latched address to an output of the input circuit arrangement, the latched address including, during a first half of the clock cycle, a read address received at a first input port, and, during a second half of the clock cycle, a write address received at a second input port, an array of single-port memory cells, the memory circuit being configured to perform read and write operations during the respective first and second halves of the clock cycle, and a decoding circuit arrangement configured to, based on the latched address at the output, activate a row of memory cells of the array during each of the first and second clock cycle halves.
    Type: Application
    Filed: December 31, 2024
    Publication date: May 1, 2025
    Inventors: XiuLi YANG, Ching-Wei WU, He-Zhou WAN, Kuan CHENG, Luping KONG
  • Publication number: 20250120185
    Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.
    Type: Application
    Filed: December 15, 2024
    Publication date: April 10, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 12271374
    Abstract: An analysis system connects to a set of data sources and perform natural language questions based on the data sources. The analysis system connects with the data sources and retrieves metadata describing data assets stored in each data source. The analysis system generates an execution plan for the natural language question. The analysis system finds data assets that match the received question based on the metadata. The analysis system ranks the data assets and presents the ranked data assets to users for allowing users to modify the execution plan. The analysis system may use execution plans of previously stored questions for executing new questions. The analysis system supports selective preprocessing of data to increase the data quality.
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: April 8, 2025
    Assignee: Promethium, Inc.
    Inventors: Kaycee Kuan-Cheng Lai, Aleksey Vinokurov, Ravikanth Kasamsetty
  • Publication number: 20250104765
    Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
  • Publication number: 20250104766
    Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
  • Publication number: 20250072042
    Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.
    Type: Application
    Filed: October 4, 2023
    Publication date: February 27, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tzu-Hsin Chen, Mei-Ling Chao, Tien-Hao Tang, Kuan-cheng Su
  • Patent number: 12211833
    Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20250031458
    Abstract: A semiconductor structure is provided in the present invention, including a substrate, a deep N-well formed in the substrate, a first well formed in the deep N-well, a first gate formed on the first well, a first source and a first drain formed respectively at two sides of the first gate in the first well, a first doped region formed in the first well, and a metal interconnect electrically connected with the first source and the first doped region, wherein an area of the deep N-well multiplied by a first parameter is a first factor, an area of the first gate multiplied by a second parameter is a second factor, and an area of the metal interconnect divided by a sum of the first factor and the second factor is less than a specification value.
    Type: Application
    Filed: September 5, 2023
    Publication date: January 23, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Lin, Wen-Chun Chang, Sung-Nien Kuo, Tzu-Chun Chen, Kuan-Cheng Su
  • Patent number: 12198754
    Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: January 14, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, Lu-Ping Kong, Kuan Cheng, He-Zhou Wan
  • Patent number: 12190033
    Abstract: A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: January 7, 2025
    Assignee: ANAGLOBE TECHNOLOGY, INC.
    Inventors: Kuan-Cheng Chen, Yan-Lin Chen, Yu-Sheng Lu, Yao-Wen Chang, Yu-Tsang Hsieh
  • Patent number: 12184285
    Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 31, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: XiuLi Yang, Kuan Cheng, He-Zhou Wan, Ching-Wei Wu, Wenchao Hao
  • Patent number: 12183432
    Abstract: A circuit includes a series of a first latch circuit, selection circuit, second latch circuit, and pre-decoder. A control circuit, based on a clock signal, outputs control signals to the selection circuit and first and second latch circuits, and, to the pre-decoder, a pulse signal including a first pulse during a first portion of a clock period in response to a read enable signal having a first logical state, and a second pulse during a second portion of the clock period in response to a write enable signal having the first logical state. Based on the control signals, the selection circuit and first and second latch circuits output read and write addresses to the pre-decoder during the respective first and second clock period portions, and the pre-decoder outputs a partially decoded address in response to each of the read address and first pulse, and the write address and second pulse.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: December 31, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED, TSMC NANJING COMPANY, LIMITED
    Inventors: XiuLi Yang, Ching-Wei Wu, He-Zhou Wan, Kuan Cheng, Luping Kong
  • Patent number: 12135337
    Abstract: A sensor assembly and sensing method is provided for proximity detection for assessing an attachment state of a sensing probe with respect to a subject. A probe is coupled to an electronic probe controller. The probe includes a proximity sensor having a passive energy storing circuit element, and a biological sensor receptacle configured to receive a biological sensor for sensing a biological characteristic of an object. The electronic probe controller excites a circuit network incorporating the proximity sensor with an excitation signal and determines a characteristic of the circuit network that is excited by the excitation signal. The electronic probe controller further generates a proximity indication indicating whether the probe is attached to the object based on the characteristic of the circuit network.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: November 5, 2024
    Assignee: The General Hospital Corporation
    Inventors: Maria A. Franceschini, Adriano Peruch, Kuan Cheng Wu, Marco Renna
  • Publication number: 20240362470
    Abstract: The application provides a panoramic perception method, system and a non-transitory computer readable medium. The panoramic perception method comprises: performing a first pretraining on a plurality of weights of a training model using the source database; performing a second pretraining with data augmentation on the plurality of weights of the training model using the source database; performing a combined training on the plurality of weights of the training model using both the source database and the target database; performing a quantization-aware training on the plurality of weights of the training model using the source database and the target database; performing a post training quantization on the plurality of weights of the training model using the target database; and performing panoramic perception by the training model.
    Type: Application
    Filed: October 3, 2023
    Publication date: October 31, 2024
    Inventors: Yu-Chen LU, Sheng-Feng YU, Wei-Cheng LIN, Chi-Chih CHANG, Pei-Shuo WANG, Kuan-Cheng LIN, Kai-Chiang WU
  • Patent number: 12125876
    Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a fin is formed on a substrate, an isolation region is formed on opposing sides of the fin. The isolation region is doped with carbon to form a doped region, and a portion of the isolation region is removed to expose a top portion of the fin, wherein the removed portion of the isolation region includes at least a portion of the doped region.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Cheng Wang, Han-Ti Hsiaw
  • Publication number: 20240302428
    Abstract: A testing device and a testing method thereof. The testing device includes a controller and a data storage device. The controller receives multiple command sequences respectively sent by application platforms through an input interface. The data storage device stores multiple circuit information corresponding to each of the application platforms and each of the command sequences corresponding to each of the application platforms. The controller, during a test period, is connected to at least one device under test through an output interface. The controller executes a test operation on the at least one device under test according to each of the circuit information corresponding to each of the application platforms and each of the command sequences corresponding to each of the application platforms.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 12, 2024
    Applicant: Winbond Electronics Corp.
    Inventor: Kuan-Cheng Chang
  • Publication number: 20240274174
    Abstract: A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.
    Type: Application
    Filed: April 25, 2024
    Publication date: August 15, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, Kuan CHENG, He-Zhou WAN, Wei-Yang JIANG
  • Patent number: 12051614
    Abstract: A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung Han Hsu, Kuan-Cheng Wang, Han-Ti Hsiaw, Shin-Yeu Tsai
  • Publication number: 20240194668
    Abstract: An electrostatic discharge protection structure includes a semiconductor substrate and a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure disposed in the semiconductor substrate. The p-type well region is located adjacent to the first n-type well region. The first p-type doped region and the second p-type doped region are located above the first n-type well region and the p-type well region, respectively. A first portion of the isolation structure is located between the first p-type doped region and the second p-type doped region in a horizontal direction. An edge of the first n-type well region is located under the first portion. A distance between the first p-type doped region and the edge of the first n-type well region in the horizontal direction is less than a length of the first portion in the horizontal direction.
    Type: Application
    Filed: February 3, 2023
    Publication date: June 13, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsuan Lin, Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 12002542
    Abstract: A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: June 4, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, Kuan Cheng, He-Zhou Wan, Wei-Yang Jiang