Patents by Inventor Kuan Cheng

Kuan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113602
    Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate laterally offset from the first semiconductor channel. A first gate structure and a second gate structure are over and laterally surround the first and second semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure. A dielectric feature over the inactive fin includes multiple layers of dielectric material formed through alternating deposition and etching steps.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei JHAN, Chih-Hao WANG, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Kuan-Ting PAN
  • Publication number: 20250112152
    Abstract: A device includes a first transistor, a second transistor, an interlayer dielectric (ILD) layer, and a backside gate rail. The first and second transistors are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source/drain epitaxial structure and a second source/drain epitaxial structure connected to the first channel layer. The second transistor includes a second channel layer, the gate structure surrounding the second channel layer, a third source/drain epitaxial structure and a fourth source/drain epitaxial structure connected to the second channel layer. A portion of the ILD layer is sandwiched between the first and third source/drain epitaxial structures. The backside gate rail is under the ILD layer and is electrically connected to the gate structure. The portion of the ILD layer is directly above the backside gate rail.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hsin-Cheng LIN, Kuan-Ying CHIU, Chee-Wee LIU
  • Patent number: 12265067
    Abstract: The disclosure describes embodiments of an apparatus including a first gas chromatograph including a fluid inlet, a fluid outlet, and a first temperature control. A controller is coupled to the first temperature control and includes logic to apply a first temperature profile to the first temperature control to heat, cool, or both heat and cool the first gas chromatograph. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: April 1, 2025
    Assignee: Tricorntech Corporation
    Inventors: Tsung-Kuan A. Chou, Shih-Chi Chu, Chia-Sheng Cheng, Li-Peng Wang, Chien-Lin Huang
  • Publication number: 20250104766
    Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
  • Publication number: 20250104765
    Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
  • Publication number: 20250098293
    Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 20, 2025
    Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG, Kuan-Lun CHENG, Guan-Lin CHEN
  • Patent number: 12255217
    Abstract: A semiconductor device includes a first type of light sensing units, where each instance of the first type of light sensing units is operable to receive a first amount of radiation; and a second type of light sensing units, where each instance of the second type of light sensing units is operable to receive a second amount of radiation, and the second type of light sensing units is arranged in an array with the first type of light sensing units to form a pixel sensor. The first amount of radiation is smaller than the second amount of radiation, and at least a first instance of the first type of light sensing units is adjacent to a second instance first type of light sensing unit.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Wen Huang, Chun-Lin Fang, Kuan-Ling Pan, Ping-Hao Lin, Kuo-Cheng Lee, Cheng-Ming Wu
  • Publication number: 20250087533
    Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.
    Type: Application
    Filed: March 28, 2024
    Publication date: March 13, 2025
    Inventors: Ming-Hsing Tsai, Ya-Lien Lee, Chih-Han Tseng, Kuei-Wen Huang, Kuan-Hung Ho, Ming-Uei Hung, Chih-Cheng Kuo, Yi-An Lai, Wei-Ting Chen
  • Patent number: 12249772
    Abstract: An electronic device is provided. The electronic device includes a metal housing, a substrate and a radiating element. The metal housing is provided with a slot, and the slot includes an opening end and a closed end. The slot has a first wall of the slot and a second wall of the slot opposite to each other at the position of the opening end. The first wall of the slot is located between the second wall of the slot and the closed end. There is a predetermined distance between the first wall of the slot and the closed end. A feeding portion of the radiating element is connected to a feeding element and a signal is fed through the feeding element, so that the radiating element is used for exciting the metal housing to generate at least one resonance frequency.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: March 11, 2025
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Chih-Feng Tai, Kuan-Hsun Lai, Kuei-Cheng Wang
  • Publication number: 20250078917
    Abstract: An SRAM cell includes a first active region, a first gate structure, a second gate structure, and a first source/drain contact region. The first gate structure is over the first active region and forms a pull-up transistor with the first active region. The second gate structure is over the first active region and forms a write-assist transistor with the first active region. The write-assist transistor and the pull-up transistor are of a same conductivity type. The first source/drain contact region is over a source/drain of the write-assist transistor and a source/drain of the pull-up transistor.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsin-Cheng LIN, Tao CHOU, Kuan-Ying CHIU, Chee-Wee LIU
  • Publication number: 20250081594
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shang-Wen CHANG, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20250068467
    Abstract: A contiguous memory allocation device includes a memory and a processor. The memory is configured to store at least one command. The processor is configured to read the at least one command to execute following steps: calculating a page thrashing value of the memory; determining a corresponding relation between the page thrashing value and a predetermined thrashing value; and deciding whether to lend a contiguous memory according to the corresponding relation.
    Type: Application
    Filed: August 23, 2024
    Publication date: February 27, 2025
    Inventors: Yi-Kuan WU, Hsiang-Wei SUNG, Meng-Sin WU, Sheng-Kai HUNG, Tsai-Chin CHENG
  • Publication number: 20250072042
    Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.
    Type: Application
    Filed: October 4, 2023
    Publication date: February 27, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tzu-Hsin Chen, Mei-Ling Chao, Tien-Hao Tang, Kuan-cheng Su
  • Publication number: 20250072054
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures over a substrate and multiple second semiconductor nanostructures over the substrate. The semiconductor device structure also includes a dielectric structure between the first semiconductor nanostructures and the second semiconductor nanostructures. The semiconductor device structure further includes a metal gate stack wrapped around the first semiconductor nanostructures and the second semiconductor nanostructures. The metal gate stack has a gate dielectric layer and a gate electrode. The gate dielectric layer extends along a sidewall of a lower portion of the dielectric structure. A topmost surface of the gate dielectric layer is between a topmost surface of the first semiconductor nanostructures and a topmost surface of the dielectric structure.
    Type: Application
    Filed: November 8, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng CHIANG, Huan-Chieh SU, Kuan-Ting PAN, Shi-Ning JU, Chih-Hao WANG
  • Patent number: 12237372
    Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Jia-Ni Yu, Chung-Wei Hsu, Chih-Hao Wang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Mao-Lin Huang
  • Patent number: 12237405
    Abstract: A method includes forming a plurality of fin structures extending along a first direction. The method includes forming a dummy fin structure disposed between two adjacent fin structures. The dummy fin structure also extends along the first direction and includes a deformable layer. The method includes recessing portions of each fin structure. The method includes forming source/drain structures over the recessed fin structures. The method includes deforming the deformable layer of the dummy fin structure to apply either a tensile stress or a compressive stress on the source/drain structures coupled to each of the two adjacent fin structures.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12237373
    Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Jia-Ni Yu, Chung-Wei Hsu, Chih-Hao Wang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Mao-Lin Huang
  • Publication number: 20250063808
    Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Inventors: KUAN-TING PAN, JIA-CHUAN YOU, CHIA-HAO CHANG, KUO-CHENG CHIANG, CHIH-HAO WANG
  • Patent number: 12224348
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a channel region of a semiconductor fin structure, a source/drain feature on a source/drain region of the semiconductor fin structure, and a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure. A top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.
    Type: Grant
    Filed: April 15, 2024
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: D1064248
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 25, 2025
    Assignee: Delta Electronics, Inc.
    Inventors: Ming-Kai Hsieh, Ching-Hsiang Huang, Po-Chun Wang, Kuan-Ting Shen, Hao-Cheng Wang