Patents by Inventor Kuan Cheng

Kuan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250072042
    Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.
    Type: Application
    Filed: October 4, 2023
    Publication date: February 27, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tzu-Hsin Chen, Mei-Ling Chao, Tien-Hao Tang, Kuan-cheng Su
  • Publication number: 20250068467
    Abstract: A contiguous memory allocation device includes a memory and a processor. The memory is configured to store at least one command. The processor is configured to read the at least one command to execute following steps: calculating a page thrashing value of the memory; determining a corresponding relation between the page thrashing value and a predetermined thrashing value; and deciding whether to lend a contiguous memory according to the corresponding relation.
    Type: Application
    Filed: August 23, 2024
    Publication date: February 27, 2025
    Inventors: Yi-Kuan WU, Hsiang-Wei SUNG, Meng-Sin WU, Sheng-Kai HUNG, Tsai-Chin CHENG
  • Publication number: 20250072054
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures over a substrate and multiple second semiconductor nanostructures over the substrate. The semiconductor device structure also includes a dielectric structure between the first semiconductor nanostructures and the second semiconductor nanostructures. The semiconductor device structure further includes a metal gate stack wrapped around the first semiconductor nanostructures and the second semiconductor nanostructures. The metal gate stack has a gate dielectric layer and a gate electrode. The gate dielectric layer extends along a sidewall of a lower portion of the dielectric structure. A topmost surface of the gate dielectric layer is between a topmost surface of the first semiconductor nanostructures and a topmost surface of the dielectric structure.
    Type: Application
    Filed: November 8, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng CHIANG, Huan-Chieh SU, Kuan-Ting PAN, Shi-Ning JU, Chih-Hao WANG
  • Patent number: 12237405
    Abstract: A method includes forming a plurality of fin structures extending along a first direction. The method includes forming a dummy fin structure disposed between two adjacent fin structures. The dummy fin structure also extends along the first direction and includes a deformable layer. The method includes recessing portions of each fin structure. The method includes forming source/drain structures over the recessed fin structures. The method includes deforming the deformable layer of the dummy fin structure to apply either a tensile stress or a compressive stress on the source/drain structures coupled to each of the two adjacent fin structures.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12237373
    Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Jia-Ni Yu, Chung-Wei Hsu, Chih-Hao Wang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Mao-Lin Huang
  • Patent number: 12237372
    Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Jia-Ni Yu, Chung-Wei Hsu, Chih-Hao Wang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Mao-Lin Huang
  • Publication number: 20250063808
    Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Inventors: KUAN-TING PAN, JIA-CHUAN YOU, CHIA-HAO CHANG, KUO-CHENG CHIANG, CHIH-HAO WANG
  • Patent number: 12224348
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a channel region of a semiconductor fin structure, a source/drain feature on a source/drain region of the semiconductor fin structure, and a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure. A top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.
    Type: Grant
    Filed: April 15, 2024
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20250048658
    Abstract: In some embodiments, the present disclosure relates to an integrated device, including a substrate; an interconnect structure disposed over the substrate, the interconnect structure including an dielectric; a first bottom electrode structure disposed in the dielectric, the first bottom electrode structure having a first width as measured between outer sidewalls of the first bottom electrode structure and a first depth as measured from an upper surface of the dielectric; and a second bottom electrode structure disposed in the dielectric and spaced apart from the first bottom electrode structure, the second bottom electrode structure having a second width as measured between outer sidewalls of the second bottom electrode structure and a second depth as measured from the upper surface of the dielectric; where the first width is greater than the second width and the first depth is greater than the second depth.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Meng-Hsien Lin, Hsing-Chih Lin, Wei-Chih Weng, Kuan-Hua Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20250046762
    Abstract: A display device is provided. The display device includes a substrate having a surface including a display area; a plurality of light-emitting diodes disposed on the display area of the substrate, wherein the light-emitting diode includes an electrode; and a plurality of bonding pads disposed on the substrate; a conductive element disposed between one of the plurality of bonding pads and the electrode of the at least one of the plurality of light-emitting diodes; and a first matrix element disposed on the substrate, wherein in a cross-sectional view, the first matrix element is disposed between adjacent two of the plurality of light-emitting diodes, and the electrode has a sidewall profile and at least a part of the sidewall profile of the electrode is in a shape of a curve.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Inventors: Yuan-Lin WU, Kuan-Feng LEE, Wei-Cheng CHU
  • Patent number: 12218164
    Abstract: A semiconductor image sensing structure includes a substrate having a first region and a second region, a metal grid in the first region, and a hybrid metal shield in the second region. The hybrid metal shield includes a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer. An included angle of the second metallization layer is between approximately 40° and approximately 60°.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Hsien Yang, Wen-I Hsu, Kuan-Fu Lu, Feng-Chi Hung, Jen-Cheng Liu, Dun-Nian Yaung, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 12218136
    Abstract: A semiconductor device includes a semiconductor fin, a gate structure, source/drain structures, and a contact structure. The semiconductor fin extends from a substrate. The gate structure extends across the semiconductor fin. The source/drain structures are on opposite sides of the gate structure. The contact structure is over a first one of the source/drain structures. The contact structure includes a semiconductor contact and a metal contact over the semiconductor contact. The semiconductor contact has a higher dopant concentration than the first one of the source/drain structures. The first one of the source/drain structures includes a first portion and a second portion at opposite sides of the fin and interfacing the semiconductor contact.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20250036977
    Abstract: An electronic device is configured to execute instructions: compiling a first AI model and second AI model(s) to a first compiled file and second compiled file(s), respectively, wherein the first compiled file comprises a first data set and a first command set, and the second compiled file(s) comprises second data set(s) and second command set(s); generating light version file(s) for the AI model(s), wherein the light version file(s) comprises the second command set(s) and data patch(es); storing the first compiled file and the light version file(s) to a storage device; loading the first compiled file from the storage device to a memory; loading the light version file(s) from the storage device to the memory; generating the second data set(s) according to the first data set and the data patch(es); and executing the second AI model(s) according to the generated second data set(s) and the second command set(s) in the memory.
    Type: Application
    Filed: June 23, 2024
    Publication date: January 30, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chia-Wei Hsu, Yu-Lung Lu, Yen-Ting Chiang, Chih-wei Chen, Yi-Cheng Lu, Jia-Sian Hong, Kuan-Yu Chen, Pei-Kuei Tsung, Hua Wu
  • Publication number: 20250040187
    Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a dielectric wall disposed over a substrate, first and second metal gate structure portions respectively disposed at either side of the dielectric wall. Each first and second metal gate structure portion includes a plurality of semiconductor layers vertically stacked and separated from each other, a high-K (HK) dielectric layer disposed to surround at least three surfaces of each of the semiconductor layers, and a gate electrode layer disposed between two neighboring semiconductor layers. The semiconductor device structure also includes a metal layer disposed on two opposing sidewalls of the dielectric wall.
    Type: Application
    Filed: December 4, 2023
    Publication date: January 30, 2025
    Inventors: Chia-Hao CHANG, Kuan-Ting PAN, Jia-Chuan YOU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250035890
    Abstract: An optical lens system includes six lens elements from an object side to an image side, the six lens elements are, in order from the object side to the image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. Each of the six lens elements has an object-side surface towards the object side and an image-side surface towards the image side. The image-side surface of the second lens element is concave in a paraxial region thereof. The third lens element has positive refractive power. The image-side surface of the fourth lens element is concave in a paraxial region thereof. The image-side surface of the sixth lens element includes at least one inflection point.
    Type: Application
    Filed: May 31, 2024
    Publication date: January 30, 2025
    Inventors: Kuan-Ting YEH, Shih-Han CHEN, Yi-Cheng LIN, Hsin-Hsuan HUANG, Yu-Han SHIH
  • Patent number: 12211921
    Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12211833
    Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20250031458
    Abstract: A semiconductor structure is provided in the present invention, including a substrate, a deep N-well formed in the substrate, a first well formed in the deep N-well, a first gate formed on the first well, a first source and a first drain formed respectively at two sides of the first gate in the first well, a first doped region formed in the first well, and a metal interconnect electrically connected with the first source and the first doped region, wherein an area of the deep N-well multiplied by a first parameter is a first factor, an area of the first gate multiplied by a second parameter is a second factor, and an area of the metal interconnect divided by a sum of the first factor and the second factor is less than a specification value.
    Type: Application
    Filed: September 5, 2023
    Publication date: January 23, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Lin, Wen-Chun Chang, Sung-Nien Kuo, Tzu-Chun Chen, Kuan-Cheng Su
  • Patent number: 12205985
    Abstract: A device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. A first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. A first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Jhan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: D1064248
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 25, 2025
    Assignee: Delta Electronics, Inc.
    Inventors: Ming-Kai Hsieh, Ching-Hsiang Huang, Po-Chun Wang, Kuan-Ting Shen, Hao-Cheng Wang