Patents by Inventor Kuan Cheng

Kuan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162218
    Abstract: An electrostatic discharge device including a gate structure, a plurality of first doped regions, and a plurality of second doped regions. The gate structure is disposed on a substrate. The gate structure includes a body part and a plurality of extension parts. The extension parts are connected with the body part, and an extension direction of the body part is different from an extension direction of the extension parts. The first doped regions are located in the substrate between the extension parts. The second doped regions are located in the substrate at two outer sides of the extension parts. The first doped regions and the second doped regions have different conductivity types.
    Type: Application
    Filed: February 6, 2023
    Publication date: May 16, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chih Hsiang Chang, Mei-Ling Chao, Yin-Chia Tsai, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20240162227
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.
    Type: Application
    Filed: November 19, 2023
    Publication date: May 16, 2024
    Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG, Kuan-Lun CHENG
  • Patent number: 11984488
    Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng
  • Publication number: 20240154043
    Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 9, 2024
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240154014
    Abstract: The present disclosure provides a forksheet structure in a semiconductor device and methods of manufacturing thereof. The forksheet structure according to the present disclosure includes a dielectric wall disposed between two channel regions inside a gate structure and without extending through the sidewall spacers to the source/drain regions. In some embodiments, a cut metal gate (CMG) dielectric structure is formed in the gate structure along with the dielectric walls. A gate dielectric layer is in contact with the dielectric wall. In some embodiments, the dielectric layer surrounds semiconductor channels in the channel region. In other embodiments, the gate dielectric layer surrounds a portion of the semiconductor channels in the channel region, for example forming a ?-shape cross sectional profile around the semiconductor channel.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 9, 2024
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi Ning JU, Chia-Hao CHANG, Chih-Hao WANG
  • Patent number: 11978678
    Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: May 7, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
  • Publication number: 20240145470
    Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Lung-Kun CHU, Mao-Lin HUANG, Chung-Wei HSU, Jia-Ni YU, Kuo-Cheng CHIANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20240142669
    Abstract: An electronic device including a protective substrate is provided. The protective substrate includes a substrate and an anti-reflection layer. The anti-reflection layer is disposed on the substrate. The anti-reflection layer includes a first sublayer to an nth sublayer sequentially arranged on the substrate, where n is greater than 1, and a product range of a thickness and a refractive index of the nth sublayer ranges from 100 nm to 170 nm.
    Type: Application
    Filed: September 21, 2023
    Publication date: May 2, 2024
    Applicants: Innolux Corporation, CARUX TECHNOLOGY PTE. LTD.
    Inventors: Kuan-Chen Chen, Liang-Cheng Ma, Ming-Er Fan
  • Publication number: 20240147405
    Abstract: A controlling method for a wireless communication device is provided. The controlling method for the wireless communication device includes: attaching a first Universal Subscriber Identity Module (USIM) to a Long-Term Evolution (LTE) network; determining whether a second USIM is camped on the LTE network; detecting whether a paging collision is happened, if the second USIM is camped on the LTE network; generating a requested International Mobile Subscriber Identity (IMSI) offset for the second USIM, if the paging collision is happened, wherein the requested IMSI offset is 1 or min(T, nB)?1, T is a default paging period and nB is a number of paging occurrences within the default paging period; transmitting an attach request with the requested IMSI offset to the LTE network for the second USIM; receiving a negotiated IMSI offset from the LTE network; and attaching the second USIM to the LTE network with the negotiated IMSI offset.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Yu LIN, Ya-ling Hsu, Wan-Ting Huang, Yi-Han CHUNG, Yi-Cheng CHEN
  • Publication number: 20240136401
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.
    Type: Application
    Filed: January 5, 2024
    Publication date: April 25, 2024
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20240128216
    Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 18, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Ching-Chun Wang, Hsiao-Hui Tseng, Chen-Jong Wang, Dun-Nian Yaung
  • Patent number: 11961900
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Teng-Chun Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11961913
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain feature on a semiconductor fin structure, a first isolation structure surrounding the semiconductor fin structure, source/drain spacers on the first isolation structure and surrounding a lower portion of the source/drain feature, a dielectric fin structure adjoining and in direct contact with the first isolation structure and one of the source/drain spacers, and an interlayer dielectric layer over the source/drain spacers and the dielectric fin structure and surrounding an upper portion of the source/drain feature.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Shi-Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11961915
    Abstract: A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface contacting the back-side source/drain contact.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shi Ning Ju, Chih-Hao Wang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Wen-Ting Lan
  • Patent number: 11961840
    Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11961763
    Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Kuan-Ting Pan, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20240120402
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
    Type: Application
    Filed: November 19, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
  • Patent number: 11953344
    Abstract: A dust-proof sensing device includes a mechanical body, a feeding path, a first photoelectric sensor disposed above the feeding path, a second photoelectric sensor disposed under the feeding path, and an upper bracket. The mechanical body has a feeding path. The upper bracket is mounted above the feeding path. The upper bracket has an upper fastening portion fastened to the mechanical body, an upper wedging portion fastened at the upper fastening portion, an L-shaped upper light guiding holder fastened at the upper fastening portion, and a first light guider fastened at the upper light guiding holder. The upper fastening portion has a first inclined section. An inner edge of an upper surface of the first inclined section is intersected with a top edge of an inner surface of the upper wedging portion to form a clamping angle.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: April 9, 2024
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: You Chung Chou, Kuan Cheng Huang
  • Publication number: 20240112959
    Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Kuan-Ting PAN, Zhi-Chang LIN, Yi-Ruei JHAN, Chi-Hao WANG, Huan-Chieh SU, Shi Ning JU, Kuo-Cheng CHIANG
  • Patent number: D1024051
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Hui-Jung Huang, Hong-Kuan Li, I-Lun Li, Ling-Mei Kuo, Kuan-Ju Chen, Fang-Ying Huang, Kai-Hung Huang, Szu-Wei Yang, Kai-Teng Cheng