Abstract: The present invention relates to a botulinum toxin type A complex, and a formulation thereof and a usage method therefor. The present invention provides the botulinum toxin type A complex, comprising an HA70 component, and an HA17 component, an HA33 component, an NTNH component, and a BoNT/A1 component, wherein the botulinum toxin complex has a molecular weight of 740-790 kDa. Compared with the existing botulinum toxin complexes, the botulinum toxin complex of the present invention is smaller in molecular weight and higher in safety, and has a comparable treatment effect.

Abstract: An atrial fibrillation prediction system is provided. The atrial fibrillation prediction system includes an electrocardiogram obtaining unit and a non-transitory machine-readable medium. The non-transitory machine-readable medium is configured for storing a program which is executed by a processing unit to obtain a prediction result. The program includes a reference database obtaining module, a reference feature selecting module, a training module, a target feature selecting module and a comparing module.

Abstract: An integrated circuit includes multiple memory cells, a first pair of complementary data lines, a second pair of complementary data lines, multiple first word lines, and multiple second word lines. The memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are coupled to the second array of memory cells. Lengths of the first pair of complementary data lines are shorter than lengths of the second pair of complementary data lines. The first word lines and the second word lines are arranged according to a predetermined ratio of a number of the first word lines to a number of the second word lines. The predetermined ratio is less than 1.

Abstract: An integrated circuit includes a plurality of memory cells, a first pair of complementary data lines, and a second pair of complementary data lines. The plurality of memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are different from the first pair of complementary data lines and are coupled to the second array of memory cells. A number of memory cells in the first array of memory cells is different from a number of memory cells in the second array of memory cells.

Abstract: A circuit includes a tracking word line, a power switch, a tracking bit line, a sense circuit. The power switch is coupled between the tracking word line and a first node. The power switch is configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted through the tracking word line to the power switch. The tracking bit line is coupled between the first node and a plurality of tracking cells in a memory array. The sense circuit is coupled between the first node and a second node. The sense circuit is configured to generate a negative bit line enable signal in response to that the voltage level on the first node is below a threshold voltage value of the sense circuit.

Abstract: A device includes memory banks, a first pair of write data wirings, a second pair of write data wirings and a global write circuit. The first pair of write data wirings is connected to a first group among the memory banks. The second pair of write data wirings is connected to a second group among the memory banks. In response to a first clock signal, the global write circuit generates a first global write signal and a first complement global write signal transmitted to the first group among the memory banks through the first pair of write data wirings. In response to a second clock signal, the global write circuit generates a second global write signal and a second complement global write signal transmitted to the second group among the memory banks through the second pair of write data wirings.

Abstract: An image rendering device and an image rendering method are disclosed. For the elements of the image rendering device, a first sensor and a second sensor are configured to sense a target object in a two-dimensional (2D) mode and three-dimensional (3D) mode to generate a first surface-color-signal, a first 3D-depth-signal, a second surface-color-signal and a second 3D-depth-signal respectively. An IR projector is configured to generate an IR-dot-pattern. A processor is configured to control the IR projector to project the IR-dot-pattern on the target object in the 3D mode, and configured to process the first surface-color-signal, the second surface-color-signal, the first 3D-depth-signal and the second 3D-depth-signal to obtain a color 3D model of the target object.

Abstract: An integrated circuit includes a first array of memory cells, a second array of memory cells, a first pair of complementary data lines, a second pair of complementary data lines, and a third pair of complementary data lines. The first pair of complementary data lines extend along the first array of memory cells, and are coupled to the first array of memory cells. The second pair of complementary data lines extend along the second array of memory cells, and are coupled to the first pair of complementary data lines. The third pair of complementary data lines extend along the second array of memory cells, and are coupled to the second array of memory cells. A number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells.

Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. The latch clock generator includes a first inverter configured to generate an inverted signal of the first enable signal, and a NAND gate coupled to the first inverter to receive the inverted signal of the first enable signal. The NAND gate is configured to generate the latched clock signal based on the clock signal and the inverted signal of the first enable signal.

Abstract: A heat dissipation device includes two connected components and a flexible metal conduit. Each connected component is selected from a manifold, a quick connector, an evaporator, a condenser or a pump. The two connected components are in communication with each other through the flexible metal conduit. The use of the flexible metal conduit is effective to absorb the designing tolerance. In addition, the flexible metal conduit is recyclable.

Abstract: An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.

Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal.

Abstract: A dynamic nameplate is provided, which includes: a base disposed on a circuit board; and a rotating member disposed on the base through a bearing, so that the rotating member can rotate relative to the base. The dynamic nameplate can provide dynamic effects without using a conventional motor.

Abstract: A sensor assembly and sensing method is provided for proximity detection for assessing an attachment state of a sensing probe with respect to a subject. A probe is coupled to an electronic probe controller. The probe includes a proximity sensor having a passive energy storing circuit element, and a biological sensor receptacle configured to receive a biological sensor for sensing a biological characteristic of an object. The electronic probe controller excites a circuit network incorporating the proximity sensor with an excitation signal and determines a characteristic of the circuit network that is excited by the excitation signal. The electronic probe controller further generates a proximity indication indicating whether the probe is attached to the object based on the characteristic of the circuit network.

Abstract: A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.

Abstract: A flexural document pick-up device includes: a feeding path comprised of a upper wall and a lower wall; a input tray arranged upstream to the feeding path; a paper feeding unit arranged partially in the feeding path; a separation roller disposed on the opposite side of the paper feeding unit; a blocking arm disposed upstream to the paper feeding unit; a securing groove arranged on the upper wall; and a guiding unit with the following portions disposed sequentially from downstream to upstream of the feeding direction: a securing section which is secured to the securing groove, a flexure section which is extended from the securing section to the feeding path, a guiding section which is connected to the flexure section and essentially parallel to the feeding path, a lifting section which is connected to the guiding section and a vertex which is arranged on the end of the lifting section.

Abstract: Apparatuses and techniques include a substrate, a controller die mounted on the substrate, fingers electrically connecting the controller die to the substrate, a spacer mounted on the substrate adjacent to the controller die, and a first memory die mounted on the spacer. The first memory die is attached to a top surface of the spacer. The spacer has a curved edge facing the controller. The curved edge may have a first curve including a first curve apex extending away from the controller, a first curve peak on one side of the first curve apex, and a second curve peak on an opposite side of the first curve apex than the first curve peak. Additional fingers connect the controller and the first memory die at a point that is aligned with the space between the first curve and a line extending from the first curve peak and the second curve peak.

Abstract: A method for building a heart rhythm classification model that is used to classify a heart rhythm of a person is provided. 12-lead ECG datasets are used to train a neural network model that includes multiple bidirectional LSTM layers. The bidirectional LSTM layers enable the neural network model to analyze the 12-lead ECG datasets in different aspects, so as to enhance classification accuracy.

Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal.

Abstract: An integrated circuit includes a first array of memory cells, a second array of memory cells, a first pair of complementary data lines, a second pair of complementary data lines, and a third pair of complementary data lines. The first pair of complementary data lines extend along the first array of memory cells, and are coupled to the first array of memory cells. The second pair of complementary data lines extend along the second array of memory cells, and are coupled to the first pair of complementary data lines. The third pair of complementary data lines extend along the second array of memory cells, and are coupled to the second array of memory cells. A number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells.