Patents by Inventor Kuan-Cheng Su
Kuan-Cheng Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170084602Abstract: An electrostatic discharge protection device includes an anode, a cathode, a negative voltage holding transistor and a positive voltage holding transistor. The anode is coupled to an input terminal, and the cathode is coupled to a ground. The negative voltage holding transistor includes an N-well. The positive voltage holding transistor includes an N-well. The N-well of the positive voltage holding transistor and the N-well of the negative voltage holding transistor are coupled together and are float. The negative voltage holding transistor and the positive voltage holding transistor are coupled between the anode and the cathode in a manner of back-to-back.Type: ApplicationFiled: October 23, 2015Publication date: March 23, 2017Inventors: Li-Cih Wang, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
-
Patent number: 9564436Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.Type: GrantFiled: November 18, 2013Date of Patent: February 7, 2017Assignee: United Microelectronics Corp.Inventors: Yung-Ju Wen, Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
-
Patent number: 9559091Abstract: A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.Type: GrantFiled: June 21, 2015Date of Patent: January 31, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
-
Publication number: 20160351558Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.Type: ApplicationFiled: May 3, 2016Publication date: December 1, 2016Inventors: Yu-Chun Chen, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
-
Patent number: 9455246Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.Type: GrantFiled: April 16, 2015Date of Patent: September 27, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
-
Publication number: 20160260700Abstract: An electrostatic discharge protection semiconductor device includes a substrate, a gate set positioned on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the drain region, and at least a second doped region formed in the substrate. The source region and the drain region include a first conductivity type, the first doped region and the second doped region include a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other. The first doped region and the second doped region are electrically connected to each other.Type: ApplicationFiled: May 29, 2015Publication date: September 8, 2016Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Chen Chang
-
Patent number: 9368484Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.Type: GrantFiled: May 28, 2015Date of Patent: June 14, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Chun Chen, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
-
Patent number: 9368500Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.Type: GrantFiled: November 5, 2013Date of Patent: June 14, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang, Kuan-Cheng Su
-
Patent number: 9343567Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.Type: GrantFiled: August 8, 2014Date of Patent: May 17, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Ning He, Jhih-Ming Wang, Lu-An Chen, Tien-Hao Tang, Kuan-Cheng Su
-
Publication number: 20160126331Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.Type: ApplicationFiled: November 26, 2014Publication date: May 5, 2016Inventors: Chi-Ju Lee, Yao-Chang Wang, Nien-Ting Ho, Chi-Mao Hsu, Kuan-Cheng Su, Main-Gwo Chen, Hsiao-Kwang Yang, Fang-Hong Yao, Sheng-Huei Dai, Tzung-Lin Li
-
Patent number: 9331161Abstract: The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure.Type: GrantFiled: November 26, 2014Date of Patent: May 3, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Ju Lee, Yao-Chang Wang, Nien-Ting Ho, Chi-Mao Hsu, Kuan-Cheng Su, Main-Gwo Chen, Hsiao-Kwang Yang, Fang-Hong Yao, Sheng-Huei Dai, Tzung-Lin Li
-
Patent number: 9331064Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.Type: GrantFiled: June 18, 2015Date of Patent: May 3, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
-
Publication number: 20160043216Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.Type: ApplicationFiled: August 8, 2014Publication date: February 11, 2016Inventors: Yi-Ning He, Jhih-Ming Wang, Lu-An Chen, Tien-Hao Tang, Kuan-Cheng Su
-
Publication number: 20150303183Abstract: A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.Type: ApplicationFiled: June 21, 2015Publication date: October 22, 2015Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
-
Publication number: 20150287838Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
-
Publication number: 20150221632Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.Type: ApplicationFiled: April 16, 2015Publication date: August 6, 2015Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
-
Patent number: 9093565Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.Type: GrantFiled: July 15, 2013Date of Patent: July 28, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
-
Publication number: 20150137255Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.Type: ApplicationFiled: November 18, 2013Publication date: May 21, 2015Applicant: United Microelectronics Corp.Inventors: Yung-Ju Wen, Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su
-
Publication number: 20150123184Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.Type: ApplicationFiled: November 5, 2013Publication date: May 7, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chang-Tzu Wang, Yu-Chun Chen, Tien-Hao Tang, Kuan-Cheng Su
-
Patent number: 8963202Abstract: A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.Type: GrantFiled: February 9, 2012Date of Patent: February 24, 2015Assignee: United Microelectronics CorporationInventors: Chang-Tzu Wang, Tien-Hao Tang, Kuan-Cheng Su