Abstract: A yield enhancement system has a fabrication line with semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line includes a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer.

Abstract: A plasma arcing sensor is used to increase the frequency of plasma arcing by way of neutralization of positive charges and negative charges. When the plasma arcing can be predicted, the process parameters to prevent from the plasma arcing can be carried out. The plasma arcing sensor comprises a top conductive layer formed over a substrate. A conductive layer is disposed between the top conductive layer and the wafer where the conductive layer and the top conductive layer are electrically isolated with dielectrics.

Abstract: A method of reducing junction capacitance of a source/drain region. A gate oxide layer is formed on a first conductive type substrate. A polysilicon layer is formed and patterned on the gate. Light second conductive type ions are implanted into the substrate with the polysilicon layer as a mask. An insulation layer is formed to cover a side wall of the polysilicon layer. A first step heavy of ion implantation with second conductive type ions is perform to the substrate using the polysilicon layer and the spacer as mask, so that a heavily doped region is formed. A second step of heavy ion implantation with the second conductive type ions is performed to the substrate using the polysilicon layer and the spacer as masks, so that the heavily doped region is broadened and deepened with a smooth ion distribution profile.

Abstract: A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer.

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract: A semiconductor fabrication method that enhances the ESD (electrostatic discharge) protection capability of an ESD protective device provided in an integrated circuit such as a mask-programmed ROM, allows the mask-programmed ROM to be downsized while still providing adequate ESD protection capability, and allows the mask-programmed ROM to be fabricated in a smaller size, while nonetheless providing adequate ESD protection capability for the internal circuit. Initially, a mask for the ion implantation process for the ROM is prepared. The mask is patterned additionally with a plurality of strips used to define breakdown voltage controlling areas in the ESD protective device. Then, the ion implantation process is performed through the mask so as to form the breakdown voltage controlling areas each beneath the drain of the n-type CMOS transistor.

Abstract: A tri-state read-only memory device and its fabrication method are disclosed herein. After a plurality of word lines are formed and spaced apart in parallel through patterning by a shielding layer, insulating blocks are formed to fill the trenches among the word lines. Then removing the shielding layer, sidewalls, of the insulating blocks are revealed, and spacers are formed on the sidewalls thereof. The spacers above the first state regions are removed to form the conductive width of the channel regions in three forms. By merely applying one code-implantation, the ROM device are coded into on of three states at the same time. In addition, the disposition of the insulating blocks by liquid-phase deposition prevents the misalignment that often occurs with the conventional method.

Abstract: A method for removing a diffusion barrier layer on pad regions and diminishing the effect of plasma ions induced when removing a photoresist layer by a plasma asher. A two stage rapid thermal processing step is applied to the partially-removed diffusion barrier layer before a metal layer is formed. The first stage lasts a longer period of time at a lower temperature, for example, in the range of between 50 and 60 seconds at a temperature of about 600.degree. C. The second stage lasts a shorter period of time at a higher temperature, for example, in the range of between 20 and 30 seconds at a temperature of about 750.degree. C.

Abstract: The invention describes recessed source/drain regions formed in trenches in the substrate that provide a smooth surface topology, smaller devils and improved device performance. The recessed source/drain regions have two conductive regions: the first upper lightly doped region on the trench sidewalls, and the second lower region under the trench bottom. In addition, two buried layers are formed between adjacent source/drain regions: a threshold voltage layer near the substrate surface and an anti-punchthrough layer formed at approximately the same depth as the lower source/drain regions on the trench bottoms. The upper lightly doped source/drain region and the anti-punchthrough layer have the effect of increasing the punchthrough voltage without increasing the threshold voltage. The upper and lower source/drain regions lower the overall resistivity of the source/drain allowing use of smaller line pitches and therefore smaller devils.

Abstract: A tri-state read-only memory device and its fabrication method are disclosed herein. After a plurality of word lines are formed and spaced apart in parallel through patterning by a shielding layer, insulating blocks are formed to fill the trenches among the word lines. Then removing the shielding layer, sidewalls of the insulating blocks are revealed, and spacers are formed on the sidewalls thereof. The spacers above the first state regions are removed to form the conductive width of the channel regions in three forms. By merely applying one code-implantation, the ROM device are coded into on of three states at the same time. In addition, the disposition of the insulating blocks by liquid-phase deposition prevents the misalignment that often occurs with the conventional method.

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract: A process for fabricating identification alphanumeric code markings on the substrate of mask ROM devices is disclosed. The fabrication process comprises first forming a deposited layer on the substrate of the mask ROM device. A photoresist layer is then formed on the deposited layer. A photomask layer by is then shaped by forming a pattern on the photoresist layer that reveals the channel regions of the memory cell transistors to be programmed into the blocking state, as well as reveals the graphical pattern of the alphanumeric code marking. An etching procedure then removes the portion of the deposited layer revealing the graphical pattern of the alphanumeric code markings. The photomask layer is then removed. A code implantation procedure may precede or follow the etching procedure to facilitate the programming of the memory cells of the mask ROM device.

Abstract: A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.

Abstract: An improved Read-Only-Memory (ROM) structure and a method of manufacturing said ROM device structure having an ultra-high-density of coded ROM cells, was achieved. The array of programmed ROM cells are composed of a single field effect transistor (FET) in each ROM cell. The improved ROM process utilizes the patterning of a ROM code insulating layer over each coded FET (cell) that is selected to remain in an off-state (nonconducting) when a gate voltage is applied. The remaining FETs (cells) have a thin gate oxide which switch to the on-state (conducting) when a gate voltage is applied. The thick ROM code insulating layer eliminates the need to code the FETs in the ROM memory cells by conventional high dose ion implantation. This eliminated the counter-doping of the buried bit lines by the implantation allowing for much tighter ground rules for the spacing between buried bit line.

Abstract: This is a method of manufacturing a multiple state MASK ROM semiconductor device on a P-type semiconductor substrate. The substrate includes an array of parallel buried bit lines oriented in a first direction. The process includes forming a gate oxide layer over the substrate including the buried bit lines; word lines over the gate oxide layer oriented orthogonally to the direction of the array of bit lines. Then form a first patterned implant mask over the device with a first set of openings through the mask. Ion implant dopant of a first dosage level through the openings in the mask to form implant doped regions of a first dosage level in the substrate. Form a second patterned implant mask over the device with a second set of openings through the mask. Then ion implant a dopant of a second dosage level through the openings in the mask to form implanted doped regions of a second dosage level in the substrate, the second dosage level being substantially different from the first dosage level.

Abstract: A multi-state memory cell for a mask ROM device. Source/drain regions are arranged on a substrate as strips extending along a first direction on the plane of the substrate and bit lines. Gate oxide layers are arranged on the substrate as strips extending along a second direction. Gate electrodes are each formed on top of each of the gate oxide layers as strips extending along the second direction. The gate oxide layers have a number of selected thickness' arranged in a differential series. Each of the transistor channel regions, together with their corresponding one of the neighboring source/drain pair, the gate oxide layer on top, and the gate electrodes further on top thereof constitute one of the memory cells that can have its threshold voltage varied among the differential series of thicknesses allowing for the storage of a multi-bit equivalent of memory content for the memory cell.

Abstract: A multi-state read-only-memory device and a method for fabricating the same is suitable for forming on a semiconductor substrate. The read-only memory device is provided with bit lines and word lines which are mutually intersecting. In accordance with the present invention, multiple polysilicon selective deposition procedures are utilized to form a plurality of protrusion portions onto the word lines but with multiple thicknesses. Then, one implantation procedure is applied to program the device into multiple states at the same time without incurring misalignment problems that result in inaccuracy.

Abstract: A method for fabricating ROM devices with self-aligned code implants comprises the steps of: forming an oxide layer over a silicon substrate; forming a plurality of deposition selecting strips over the oxide layer; forming a dielectric between the plurality of deposition selecting strips to thereby produce a plurality of dielectric strips; removing the deposition selecting strips; forming a number of code diffusion regions in the silicon substrate; and forming a plurality of word lines between the plurality of dielectric strips. Since the code diffusion regions are formed by implanting ions through the dielectric strips, the shielding of the dielectric strips can prevent the outspreading of impurities due to code mask mis-alignment. Therefore, the positions of code diffusion regions can be well controlled beneath the word lines.

Abstract: A method of fabricating memory cells of a mask ROM device. A plurality of source/drain regions extending along a first direction is formed by implanting impurities into a semiconductor substrate, constituting bit lines of the memory cells. A code oxide layer is formed on a designated area of the semiconductor substrate defined by a barrier layer using a liquid-phase deposition process, whereby a multi-state mask ROM is fabricated by repeatedly performing the liquid-phase deposition process to form a series of coding oxide layers having increasing thicknesses. A gate oxide layer is formed on a portion of the semiconductor substrate not covered by the coding oxide layers. The thickness of the gate oxide layer is smaller than that of the coding oxide layers. A plurality of gate electrodes extending along a second direction orthogonal to the first direction is formed by depositing and patterning a conducting layer on the coding oxide layer and the gate oxide layer, constituting word lines of said memory cells.

Abstract: A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.