Abstract: The disclosure relates to methods for determining an endometrial status using a sample, for example, a blood plasma sample, from a subject, comprising: (a) performing an assay on the blood sample from the subject to determine a miRNA expression profile, wherein the miRNA expression profile comprises expression levels of a plurality of miRNA and (b) analyzing the miRNA expression profile to obtain a predictive score using a computer-based machine-learning model.

Abstract: A controller for a power supply device includes a transmission terminal, first and second memory circuits, a determining circuit, and a control circuit. The determining circuit generates a first mode signal when an input voltage value is lower than a reference voltage value and generates a second mode signal when the input voltage value is greater than or equal to the reference voltage value. The control circuit enters a first mode and a second mode in response to the first mode signal and the second mode signal, respectively. The control circuit writes a control parameter from the transmission terminal into the first memory circuit in the first mode and uses the control parameter in the second mode to test the power supply device. When the control parameter meets an expected function of the power supply device, the control circuit writes the control parameter into the second memory circuit.

Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A speaker is provided and includes a first speaker body, a second speaker body, a speaker component, and a sound transmission member. The first speaker body has a first chamber. The second speaker body has a second chamber. The second speaker body is received in the first chamber and defines a resonant cavity in the first chamber. The speaker component is disposed on the second speaker body and includes a supporting member, a magnet, a coil, and a diaphragm. Two ends of the supporting member are respectively inserted into the second chamber and fixed on the second speaker body. The magnet is disposed in the supporting member. The diaphragm is disposed on the supporting member and abuts against the second speaker body. The coil is received in the magnet and is connected to the diaphragm. The sound transmission member is coaxially disposed in the resonant cavity with the speaker component.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Abstract: A method for fabricating a semiconductor structure is disclosed. A bit line is formed on a substrate. The bit line comprises a tungsten layer and cap layer on the tungsten layer. A low-temperature physical vapor deposition (PVD) process is performed to deposit a silicon nitride spacer layer covering the bit line and the substrate. The silicon nitride spacer layer is in direct contact with the tungsten layer. The low-temperature PVD process is performed at a temperature ranging between 200˜400° C.

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

Abstract: A semiconductor structure includes a substrate having thereon a dielectric layer. An opening is formed in the dielectric layer. The opening includes a bottom surface and a sidewall surface. A diffusion barrier layer is conformally disposed along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally disposed on the diffusion barrier layer. A bulk metal layer is disposed on the nucleation metal layer. A film-growth retarding layer is disposed between the nucleation metal layer and the bulk metal layer.

Abstract: A test structure for electron beam inspection and a method for defect determination using electron beam inspection are provided. The test structure for electron beam inspection includes a semiconductor substrate, at least two conductive regions disposed on the semiconductor substrate, a connection structure disposed on the two conductive regions, and a cap dielectric layer disposed on the connection structure. The method for defect determination using the electron beam inspection includes the following steps. An electron beam inspection is preformed to a test structure with an instant detector and a lock-in amplifier. Signals received by the detector within a period of time are amplified by the lock-in amplifier. A defect in the test structure is determined by monitoring the signals received by the detector and amplified by the lock-in amplifier. The inspection accuracy is improved by the test structure and the method for defect determination in the present invention.

Abstract: A test structure for electron beam inspection and a method for defect determination using electron beam inspection are provided. The test structure for electron beam inspection includes a semiconductor substrate, at least two conductive regions disposed on the semiconductor substrate, a connection structure disposed on the two conductive regions, and a cap dielectric layer disposed on the connection structure. The method for defect determination using the electron beam inspection includes the following steps. An electron beam inspection is preformed to a test structure with an instant detector and a lock-in amplifier. Signals received by the detector within a period of time are amplified by the lock-in amplifier. A defect in the test structure is determined by monitoring the signals received by the detector and amplified by the lock-in amplifier. The inspection accuracy is improved by the test structure and the method for defect determination in the present invention.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Abstract: A semiconductor structure includes a substrate having thereon a dielectric layer. An opening is formed in the dielectric layer. The opening includes a bottom surface and a sidewall surface. A diffusion barrier layer is conformally disposed along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally disposed on the diffusion barrier layer. A bulk metal layer is disposed on the nucleation metal layer. A film-growth retarding layer is disposed between the nucleation metal layer and the bulk metal layer.