Patents by Inventor Kuan Fu Chen
Kuan Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240069618Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
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Publication number: 20240072115Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.Type: ApplicationFiled: February 13, 2023Publication date: February 29, 2024Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
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Publication number: 20230104982Abstract: A flash memory and an erase method thereof are provided. The flash memory includes at least a memory array and a memory control circuit. The memory control circuit biases plural word lines, a common source line and a global bit line included in the memory array to erase plural memory cells in the flash memory. The method comprises grouping the plural word lines into plural word line groups according to erase depths corresponding to each word line; generating an erase voltage and plural multiple-step word line erase voltages; applying the erase voltage from at least one of the common source line and the global bit line; and during a period when the erase voltage is applied, the plural multiple-step word line erase voltages is respectively applied to the plural word line groups, wherein the plural multiple-step word line erase voltages is one-by-one corresponding to the plural word line groups.Type: ApplicationFiled: October 4, 2021Publication date: April 6, 2023Applicant: MACRONIX International Co., Ltd.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Publication number: 20220366212Abstract: A method for fault diagnosis in a communication network is to be implemented by a processor. The method includes obtaining key performance indicator (KPI) data related to the communication network, performing a deep-learning-based classification algorithm by using the KPI data as input to a deep neural network model, and determining, based on output of the deep neural network model after performing the deep-learning-based classification algorithm, at least one type of network condition the communication network currently satisfies, and a severity level of the at least one type of network condition when the output of the deep neural network model contains information related to severity levels of the at least one type of network condition.Type: ApplicationFiled: July 28, 2021Publication date: November 17, 2022Applicant: National Yang Ming Chiao Tung UniversityInventors: Ta-Sung Lee, Yen-Jung Wu, Kuan-Fu Chen, Ting-Yen Kuo
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Patent number: 11145373Abstract: A method for programming a memory device and a memory system are provided, wherein the method for programming the memory device includes steps below. First, a program command is proposed. Second, a width of a pulse about to provide to strings of memory cells of the memory device is determined according to a temperature data of the memory device. Then, the pulse is provided to the strings of memory cells to start doing a program operation. The width of the pulse becomes narrower as a temperature of the memory device is raised.Type: GrantFiled: May 22, 2020Date of Patent: October 12, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Patent number: 11056205Abstract: A memory device and a write method thereof are provided. A control circuit performs a first write operation and a first write verification operation on a plurality of memory cells of a non-volatile memory, and after the plurality of memory cells pass the first write verification operation, the control circuit performs a second write verification operation on target memory cells corresponding to at least one target threshold voltage in the plurality of memory cells, and when a failure bit count of the target memory cells is not less than a preset number of bits, the control circuit performs a second write operation and a third write verification operation on the plurality of memory cells.Type: GrantFiled: June 22, 2020Date of Patent: July 6, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Patent number: 10714197Abstract: A memory device and a program verification method thereof are provided. The write verification method includes: reading a previous page to obtain first read data, writing input data to a current page, reading the previous page or the current page to obtain second read data, and analyzing at least one of the first read data and the second read data to determine whether to back up at least one of the first read data and the input data to a redundant block of the memory device.Type: GrantFiled: April 18, 2019Date of Patent: July 14, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Patent number: 10665303Abstract: Methods, systems and apparatus for effectively erasing blocks with few programmed pages are provided. In one aspect, a system includes a memory and a controller coupled to the memory. The memory includes blocks each having pages. The controller is configured to determine whether a threshold page with a particular page number in a block of the memory is programmed, to erase the block according to a normal erase action in response to determining that the threshold page is programmed, and to erase the block according to a particular erasing action that is configured to erase the block deeper than the normal erase action in response to determining that the threshold page is not programmed. The particular erasing action can include pre-programming the block before erasing the block, decreasing an erase verify voltage before erasing the block, or adding one or more erasing pulses with a new erasing voltage.Type: GrantFiled: May 10, 2019Date of Patent: May 26, 2020Assignee: Macronix International Co., Ltd.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Patent number: 10460808Abstract: Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.Type: GrantFiled: October 25, 2017Date of Patent: October 29, 2019Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Publication number: 20190122735Abstract: Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.Type: ApplicationFiled: October 25, 2017Publication date: April 25, 2019Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Patent number: 10026490Abstract: A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse.Type: GrantFiled: October 7, 2016Date of Patent: July 17, 2018Assignee: MACRONIX International Co., Ltd.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Publication number: 20180061503Abstract: A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse.Type: ApplicationFiled: October 7, 2016Publication date: March 1, 2018Applicant: MACRONIX International Co., Ltd.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Patent number: 9779820Abstract: A non-volatile memory and a programming method thereof are provided. The programming method for the non-volatile memory includes: setting at least one first isolation cell between a first side cell and at least one first pass cell of an inhibited memory string; cutting off the at least one first isolation cell and providing a pre-boosting voltage to a word line of the first side cell and at a first time point; turning on the at least one first isolation cell at a second time point for transporting the pre-boosting potential to channels of the at least one first pass cell and a primary cell at a second time period; and providing a boosting voltage to word lines of the at least one first pass cell during a boosting time period.Type: GrantFiled: February 23, 2017Date of Patent: October 3, 2017Assignee: MACRONIX International Co., Ltd.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Patent number: 9613702Abstract: A memory device including multiple word lines, multiple bit lines and a memory cell array is provided. The word lines intersect the bit lines, and an included angle between the word lines and the bit lines is not a right angle. The memory cell array includes multiple memory cells respectively disposed at the intersections of the word lines and the bit lines. Each row of the memory cells is electrically connected to one of the word lines, and each column of the memory cells is electrically connected to one of the bit lines.Type: GrantFiled: December 31, 2015Date of Patent: April 4, 2017Assignee: MACRONIX International Co., Ltd.Inventors: Ya-Jui Lee, Kuan-Fu Chen
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Patent number: 9543001Abstract: First threshold voltages of one or more memory cells in a memory array are obtained. For each memory cell in the one or more memory cells, a target threshold voltage for the memory cell is identified. A number of programming shots to reach the target threshold voltage of the memory cell is determined based on the first threshold voltage of the memory cell. Respective number of programming shots, which are determined for the one or more memory cells, are applied to the one or more memory cells. Whether respective target threshold voltages for the one or more memory cells are reached is verified upon applying the respective number of programming shots to the one or more memory cells.Type: GrantFiled: December 31, 2015Date of Patent: January 10, 2017Assignee: Macronix International Co., Ltd.Inventors: Ya Jui Lee, Kuan Fu Chen
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Publication number: 20160307636Abstract: Methods and apparatuses are contemplated herein for enhancing the read performance and data retention of nonvolatile memory devices. In an example embodiment, a method is provided for controlling a nonvolatile memory device that includes a matrix of memory cells, wherein each memory cell in the matrix includes a programmable floating gate. The method includes programming a floating gate of a first memory cell of the nonvolatile memory device, and shifting a voltage of the floating gate of the first memory cell of the nonvolatile memory device by creating a coupling effect that impacts the floating gate of the first memory cell. In this regard, the method may include programming one or more nearby memory cells, in which case the coupling effect may comprise a floating gate coupling effect between the first memory cell and the one or more nearby memory cells.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: Ya Jui Lee, Kuan Fu Chen
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Patent number: 9437319Abstract: Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a non-volatile memory device comprising a set of cells, each cell associated with a bit line; shooting a programming voltage across each cell; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based at least in part on the detected threshold voltage for each cell; and shooting the programming voltage until the threshold voltage for each cell is greater than a verify voltage. For each shot a fast bit line bias is applied to the bit line associated each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.Type: GrantFiled: June 25, 2015Date of Patent: September 6, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Atsuhiro Suzuki, Ya Jui Lee, Kuan Fu Chen, Chih-Wei Lee
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Patent number: 9424926Abstract: A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided.Type: GrantFiled: February 4, 2016Date of Patent: August 23, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ya Jui Lee, Kuan Fu Chen
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Publication number: 20160155508Abstract: A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided.Type: ApplicationFiled: February 4, 2016Publication date: June 2, 2016Inventors: Ya Jui Lee, Kuan Fu Chen
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Patent number: RE46970Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: GrantFiled: July 11, 2016Date of Patent: July 24, 2018Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen