Patents by Inventor Kuan Fu Chen
Kuan Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9286984Abstract: A nonvolatile semiconductor device is provided that includes a substrate and a plurality of blocks forming a string. Each block is positioned on the substrate and includes a plurality of word lines disposed on the substrate. The string includes a single ground select line disposed at one side of the plurality of blocks, and a single string select line is disposed at another side of the plurality of blocks. In some embodiments, the word lines of the plurality of blocks define gaps separating each block of the string from neighboring blocks of the string. One or more dummy word lines may be disposed in each gap between blocks of the string. Corresponding methods of manufacturing the nonvolatile semiconductor device and manipulating the nonvolatile semiconductor device are provided.Type: GrantFiled: July 7, 2014Date of Patent: March 15, 2016Assignee: Macronix International Co., Ltd.Inventors: Ya Jui Lee, Kuan Fu Chen
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Patent number: 9036393Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: GrantFiled: October 25, 2013Date of Patent: May 19, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen
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Patent number: 8836004Abstract: A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.Type: GrantFiled: March 15, 2010Date of Patent: September 16, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Yu-Fong Huang, I-Shen Tsai, Shang-Wei Lin, Miao-Chih Hsu, Kuan-Fu Chen
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Patent number: 8779500Abstract: A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions.Type: GrantFiled: January 22, 2010Date of Patent: July 15, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Yu-Fong Huang, Miao-Chih Hsu, Kuan-Fu Chen, Tzung-Ting Han
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Publication number: 20140050006Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: ApplicationFiled: October 25, 2013Publication date: February 20, 2014Applicant: MACRONIX International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen
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Patent number: 8593850Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: GrantFiled: December 30, 2008Date of Patent: November 26, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen
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Patent number: 8552528Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: GrantFiled: September 22, 2011Date of Patent: October 8, 2013Assignee: Macronix International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming Shang Chen
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Patent number: 8183106Abstract: A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.Type: GrantFiled: July 26, 2006Date of Patent: May 22, 2012Assignee: Macronix International Co., Ltd.Inventors: Kuan Fu Chen, Yin Jen Chen, Meng Hsuan Weng, Tzung Ting Han, Ming Shang Chen, Chun Pei Wu
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Publication number: 20120008363Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: ApplicationFiled: September 22, 2011Publication date: January 12, 2012Applicant: Macronix International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming Shang Chen
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Publication number: 20110220986Abstract: A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.Type: ApplicationFiled: March 15, 2010Publication date: September 15, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Fong Huang, I-Shen Tsai, Shang-Wei Lin, Miao-Chih Hsu, Kuan-Fu Chen
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Publication number: 20110180864Abstract: A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions.Type: ApplicationFiled: January 22, 2010Publication date: July 28, 2011Applicant: MACRONIX International Co., Ltd.Inventors: YU-FONG HUANG, Miao-Chih Hsu, Kuan-Fu Chen, Tzung-Ting Han
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Patent number: 7888272Abstract: A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.Type: GrantFiled: December 12, 2006Date of Patent: February 15, 2011Assignee: Macronix International Co. Ltd.Inventors: Kuan Fu Chen, Yin Jen Chen, Tzung Ting Han, Ming-Shang Chen, Shih Chin Lee
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Patent number: 7671278Abstract: Provided herewith a cable (1, 2) with EMI suppressing arrangement which comprises a conductive wire (10) and an insulative layer (20) enveloping over the wire. A braided metal layer (30) envelops over the insulative layer, and a magnetic layer (40, 501) is arranged thereover. And an insulative jacket (50, 502) envelops over the magnetic layer.Type: GrantFiled: October 31, 2007Date of Patent: March 2, 2010Assignee: Hon Hai Precision Ind. Co., LtdInventors: Jen-Guo Fong, Hsi-Fu Lee, Kuan-Fu Chen
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Publication number: 20090116274Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: ApplicationFiled: December 30, 2008Publication date: May 7, 2009Applicant: MACRONIX International Co., Ltd.Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen
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Patent number: 7515158Abstract: A configurable memory system provides a high bandwidth, low latency, no wait state data path to a memory system functioning as a frame buffer for a digital video processing system. The configurable memory system has configurable channels that are programmable to control the access pattern of the memory controller. Once the configurable channels are programmed, the memory controller can generate the necessary address, timing, and control signals for selectively writing the data to and reading the data from the selected blocks of the array of memory devices continuously access the memory and move the data to the channel buffers. The channel buffer receives, retains, and transfers a defined segment of the data as defined by the segment pattern between the processing system and the array of memory devices, such that the processing system is able to transfer and receive the data continuously according to data requirements of the processing system.Type: GrantFiled: June 22, 2005Date of Patent: April 7, 2009Assignee: Etron Technology, Inc.Inventors: Peter Chang, Kuan Fu Chen
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Patent number: 7486534Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.Type: GrantFiled: December 8, 2005Date of Patent: February 3, 2009Assignee: MACRONIX International Co., Ltd.Inventors: Kuan Fu Chen, Yin Jen Chen, Tzung Ting Han, Ming Shang Chen
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Publication number: 20080138998Abstract: A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.Type: ApplicationFiled: December 12, 2006Publication date: June 12, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Kuan Fu Chen, Yin Jen Chen, Tzung Ting Han, Ming-Shang Chen, Shih Chin Lee
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Publication number: 20080099239Abstract: Provided herewith a cable (1, 2) with EMI suppressing arrangement which comprises a conductive wire (10) and an insulative layer (20) enveloping over the wire. A braided metal layer (30) envelops over the insulative layer, and a magnetic layer (40, 501) is arranged thereover. And an insulative jacket (50, 502) envelops over the magnetic layer.Type: ApplicationFiled: October 31, 2007Publication date: May 1, 2008Inventors: Jen-Guo Fong, Hsi-Fu Lee, Kuan-Fu Chen
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Publication number: 20080026527Abstract: A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.Type: ApplicationFiled: July 26, 2006Publication date: January 31, 2008Applicant: Macronix International Co., Ltd.Inventors: Kuan Fu Chen, Yin Jen Chen, Meng Hsuan Weng, Tzung Ting Han, Ming Shang Chen, Chun Pei Wu