Patents by Inventor Kuan Hua Tan
Kuan Hua Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947995Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.Type: GrantFiled: May 19, 2020Date of Patent: April 2, 2024Assignee: Intel CorporationInventors: Kuan Hua Tan, Sahar Khalili, Eng Hun Ooi, Shrinivas Venkatraman, Dimpesh Patel
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Patent number: 11907035Abstract: An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.Type: GrantFiled: May 15, 2020Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Ang Li, David J. Harriman, Kuan Hua Tan
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Patent number: 11704275Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.Type: GrantFiled: July 28, 2021Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Kuan Hua Tan, Eng Hun Ooi, Ang Li
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Publication number: 20220197519Abstract: A multi-level memory architecture scheme to dynamically balance a number of parameters such as power, thermals, cost, latency and performance for memory levels that are progressively further away from the processor in the platform based on how applications are using memory levels that are further away from processor cores. In some examples, the decision making for the state of the far memory (FM) is decentralized. For example, a processor power management unit (p-unit), near memory controller (NMC), and/or far memory host controller (FMHC) makes decisions about the power and/or performance state of the FM at their respective levels. These decisions are coordinated to provide the most optimum power and/or performance state of the FM for a given time. The power and/or performance state of the memories adaptively change to changing workloads and other parameters even when the processor(s) is in a particular power state.Type: ApplicationFiled: December 19, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Chia-Hung Kuo, Anoop Mukker, Eng Hun Ooi, Avishay Snir, Shrinivas Venkatraman, Kuan Hua Tan, Wai Ben Lin
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Publication number: 20210357350Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.Type: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Applicant: Intel CorporationInventors: Kuan Hua Tan, Eng Hun Ooi, Ang Li
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Patent number: 11080223Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.Type: GrantFiled: July 17, 2019Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Kuan Hua Tan, Eng Hun Ooi, Ang Li
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Patent number: 11038749Abstract: A handshake communication mechanism between a host and an end-point device permits multiple Base Address Registers (BAR registers) to be configured to size or resize the mapped address spaces associated with each BAR register. In one embodiment, the handshake communication mechanism includes a single address space reconfiguration request which may be transmitted in a single transaction layer packet, to request the configuration of multiple BAR registers of an end-point device. Other features and advantages may be realized, depending upon the particular application.Type: GrantFiled: December 24, 2018Date of Patent: June 15, 2021Assignee: Intel CorporationInventors: Ang Li, Eng Hun Ooi, Kuan Hua Tan
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Patent number: 10977197Abstract: Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.Type: GrantFiled: March 28, 2019Date of Patent: April 13, 2021Assignee: Intel CorporationInventors: Kuan Hua Tan, Ang Li, Eng Hun Ooi
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Patent number: 10942672Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.Type: GrantFiled: May 24, 2019Date of Patent: March 9, 2021Assignee: Intel CorporationInventors: Shrinivas Venkatraman, Eng Hun Ooi, Sahar Khalili, Dimpesh Patel, Kuan Hua Tan
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Publication number: 20200278733Abstract: An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.Type: ApplicationFiled: May 15, 2020Publication date: September 3, 2020Applicant: Intel CorporationInventors: Ang Li, David J. Harriman, Kuan Hua Tan
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Publication number: 20200278883Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.Type: ApplicationFiled: May 19, 2020Publication date: September 3, 2020Inventors: Kuan Hua TAN, Sahar KHALILI, Eng Hun OOI, Shrinivas VENKATRAMAN, Dimpesh PATEL
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Publication number: 20190340148Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.Type: ApplicationFiled: July 17, 2019Publication date: November 7, 2019Applicant: Intel CorporationInventors: Kuan Hua Tan, Eng Hun Ooi, Ang Li
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Publication number: 20190278513Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.Type: ApplicationFiled: May 24, 2019Publication date: September 12, 2019Inventors: Shrinivas Venkatraman, Eng Hun Ooi, Sahar Khalili, Dimpesh Patel, Kuan Hua Tan
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Publication number: 20190220422Abstract: Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.Type: ApplicationFiled: March 28, 2019Publication date: July 18, 2019Applicant: Intel CorporationInventors: Kuan Hua Tan, Ang Li, Eng Hun Ooi
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Publication number: 20190132198Abstract: A handshake communication mechanism between a host and an end-point device permits multiple Base Address Registers (BAR registers) to be configured to size or resize the mapped address spaces associated with each BAR register. In one embodiment, the handshake communication mechanism includes a single address space reconfiguration request which may be transmitted in a single transaction layer packet, to request the configuration of multiple BAR registers of an end-point device. Other features and advantages may be realized, depending upon the particular application.Type: ApplicationFiled: December 24, 2018Publication date: May 2, 2019Inventors: Ang LI, Eng Hun OOI, Kuan Hua TAN
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Publication number: 20190114281Abstract: Systems, methods, and device can involve an application layer logic implemented at least partially in hardware circuitry; a first port for transmitting information across a multi-lane link, the first port comprising a protocol stack; a memory element, the memory element comprising mapping between an event identifier value and an event identifier carrier value, the event identifier identifying an event to be carried out by the application layer logic across the multi-lane link, the event identifier carrier value mapped to the event identifier, the application layer logic to transmit the event identifier carrier value across the link prior to executing the event.Type: ApplicationFiled: December 13, 2018Publication date: April 18, 2019Inventors: Ang Li, Kuan Hua Tan
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Publication number: 20190095554Abstract: Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Eng Hun Ooi, Su Wei Lim, Kuan Hua Tan, Prashanth Kalluraya
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Publication number: 20190042155Abstract: Systems, apparatuses and methods may provide for technology to add non-address metadata to a memory address field of a transaction layer packet (TLP), wherein the non-address metadata includes one or more vendor-specific attributes. Additionally, the technology may coordinate between a transmitter and a receiver to prevent the TLP from violating an address boundary constraint associated with an interface. In one example, the address boundary constraint prohibits an address and length combination of the TLP from crossing a 4-KB boundary.Type: ApplicationFiled: May 14, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Eng Hun Ooi, Shrinivas Venkatraman, Kuan Hua Tan, Ang Li, Sahar Khalili, Su Wei Lim, Robert Royer, JR.
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Patent number: 10114790Abstract: An apparatus and method for port mirroring in a plurality of Peripheral Component Interconnect express (PCIe) interfaces includes, for each PCIe interface, output transmission ports for transmitting data to a central processing unit (CPU), receiving input ports for receiving data from the CPU, port-mirror-in (PM_IN) ports, and port-mirror-out (PM_OUT) ports provided in a PHY layer instance. The PM_OUT ports of each PHY layer instance is coupled to the PM_IN ports of a next PHY layer instance such that the PHY layer instances of the plurality of PCIe interfaces are connected in a ring bus architecture for mirroring one or more ports of the output transmission ports or the receiving input ports of a first active PHY layer instance can be mirrored to output transmission ports of a second PHY layer instance.Type: GrantFiled: August 8, 2016Date of Patent: October 30, 2018Assignee: Microsemi Solutions (U.S.), Inc.Inventors: Kiran Hanchinal, Kuan Hua Tan, Richard David Sodke, Gregory Arthur Tabor
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Patent number: 9880949Abstract: A PCIe bus adapted for cross clock compensation of asynchronous clocks includes one or more PHY data ports provided in a PHY layer having a transmit clock (TCLK) for timing data transmitted to a peripheral device and a receive clock (RCLK) for timing data received from the peripheral device, one or more media access control (MAC) ports provided in a MAC layer having an interface clock (PCLK) for timing data transmitted to the PHY layer and data received from the PHY layer, wherein the PCLK and one or both of the TCLK and the RCLK are asynchronous, and one or more backpressure ports at an interface between the PHY layer and the MAC layer for controlling reading and writing of one of the PHY layer and the MAC layer. In some aspects, the PCLK frequency is set to be always greater than a maximum frequency of the RCLK and the TCLK.Type: GrantFiled: December 11, 2015Date of Patent: January 30, 2018Assignee: Microsemi Solutions (U.S.), Inc.Inventors: Kiran Hanchinal, Kuan Hua Tan, Richard David Sodke, Mansi Mehrotra