Abstract: An apparatus and method for port mirroring in a plurality of Peripheral Component Interconnect express (PCIe) interfaces includes, for each PCIe interface, output transmission ports for transmitting data to a central processing unit (CPU), receiving input ports for receiving data from the CPU, port-mirror-in (PM_IN) ports, and port-mirror-out (PM_OUT) ports provided in a PHY layer instance. The PM— OUT ports of each PHY layer instance is coupled to the PM_IN ports of a next PHY layer instance such that the PHY layer instances of the plurality of PCIe interfaces are connected in a ring bus architecture for mirroring one or more ports of the output transmission ports or the receiving input ports of a first active PHY layer instance can be mirrored to output transmission ports of a second PHY layer instance.

Abstract: The disclosure generally relates to a PCIe switch that includes a selectively transparent bridge that selectively allows transactions to traverse between multiple PCIe domains without the encumbrance of each root complex entity requiring knowledge of the selectively transparent bridge. The bridge that enables the transactions is invisible to the root complex entity in a host and drive switch domain of the PCIe switch. No address translation of the transactions is required because the drive switch domain address map is a subset of the host switch domain address map. The bridge allows for extremely low latency transactions between host systems and storage drives because the bridge allows the storage drive to read the Direct Memory Access (DMA) Scatter-Gather List (SGL) directly from host memory. The bridge also allows I/O data reads and writes from the storage drive directly to the host memory without store and forward within a RAID controller's memory.

Abstract: The disclosure generally relates to a PCIe switch that includes a selectively transparent bridge that selectively allows transactions to traverse between multiple PCIe domains without the encumbrance of each root complex entity requiring knowledge of the selectively transparent bridge. The bridge that enables the transactions is invisible to the root complex entity in a host and drive switch domain of the PCIe switch. No address translation of the transactions is required because the drive switch domain address map is a subset of the host switch domain address map. The bridge allows for extremely low latency transactions between host systems and storage drives because the bridge allows the storage drive to read the Direct Memory Access (DMA) Scatter-Gather List (SGL) directly from host memory. The bridge also allows I/O data reads and writes from the storage drive directly to the host memory without store and forward within a RAID controller's memory.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: A method and apparatus for queue-ordering commands in multi-engines, multi-queues and/or multi-flows environment is provided. Commands from single/multiple queues and multi-flows are processed by multi-engines with different processing time and/or out of order, which breaks sequential order of commands from same input queue and commands are distributed across multiple engines' output buffer after processing. Processed commands are stored in dedicated command output buffer associated with each engine temporarily. The processed commands are re-ordered while writing out. Also commands can be scheduled to idle engines to achieve maximum throughput, thus utilizing the engines in an optimal manner.

Abstract: A Galois Field multiplier circuit for multiplying two polynomials (multiplicands). The multiplier circuit can use any arbitrary primitive polynomial to preserve the Galois Field. The multiplier circuit includes at least one logic unit that receives as a first input one of the multiplicands and shift the multiplicand in question by 1 bit to the left. The logic unit receives as a second input a pre-determined primitive polynomial and multiplies the primitive polynomial by the highest bit of the multiplicand received at the other input of the logic unit. The bit-shifted multiplicand is XOR-ed with the primitive polynomial multiplied the highest bit of the multiplicand and the result of the XOR operation is provided to a second logic circuit that completes the multiplication of the two polynomials.

Abstract: A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arbitration of connection requests to be setup or removed among multiple end devices and expander devices so as to increase system performance and reduce hardware cost in a standard compliant manner.

Abstract: A method and system are provided for broadcast message filtering in SAS expanders. Common SAS topology defined by ANSI T10 specification only supports spanning tree topology (without loops) interconnection among multiple end devices and expander devices. Broadcast message filtering provides a mechanism to selectively discard broadcast messages, or primitives, in the SAS expanders to break the infinite loop path that broadcast primitives can traverse. This enables new SAS physical topologies with loops that are otherwise difficult or impossible to realize using SAS expanders that handle primitive broadcasts according to the definition of the SAS standard. By allowing redundant paths in a SAS topology, the problem of infinite broadcast flooding in SAS topology is reduced. Selectively forwarding broadcast messages can be based on whether the broadcast was originated at the source phy, or received by the source phy, or based on whether the source phy is a filtered phy.

Abstract: A method and apparatus are provided for finding the maxima and minima from a set of inputs data. Given a master set K[0 . . . N?1] of N keys, the current invention can pre-compute a comparison matrix, find the maximum key KMAX or minimum key KMIN from the master set K[0 . . . N?1] and indicate the key position index PMAX of the maximum key or PMIN of the minimum key. Given a subset S[0 . . . M?1] of M keys where the subset S[0 . . . M?1] belongs to the master set K[0 . . . N?1], the current invention can also find the maximum key SMAX or minimum key SMIN from the subset S[0 . . . M?1] and indicate the reference key position index PMAX of the maxima SMAX or PMIN of the minima SMIN in the master set K[0 . . . N?1]. The current invention can also find a specific rank of key (example 5th largest key or 6th smallest key) and return the reference key index position in the master set K[0 . . . N?1].

Abstract: A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arbitration of connection requests to be setup or removed among multiple end devices and expander devices so as to increase system performance and reduce hardware cost in a standard compliant manner.