Patents by Inventor Kuan Huang
Kuan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136221Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee
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Publication number: 20240126712Abstract: A semiconductor package includes multiple dies that share the same package pin. An output enable register provided on each die is used to select the die that drives an output to the shared pin. A hardware arbitration circuit ensures that two or more dies do not drive an output to the shared pin at the same time.Type: ApplicationFiled: December 21, 2023Publication date: April 18, 2024Inventors: YULEI SHEN, TYRONE TUNG HUANG, CHEN-KUAN HONG
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Publication number: 20240095927Abstract: A computer-implemented method for partially supervised image segmentation having improved strong mask generalization includes obtaining, by a computing system including one or more computing devices, a machine-learned segmentation model, the machine-learned segmentation model including an anchor-free detector model and a deep mask head network, the deep mask head network including an encoder-decoder structure having a plurality of layers. The computer-implemented method includes obtaining, by the computing system, input data including tensor data. The computer-implemented method includes providing, by the computing system, the input data as input to the machine-learned segmentation model. The computer-implemented method includes receiving, by the computing system, output data from the machine-learned segmentation model, the output data including a segmentation of the tensor data, the segmentation including one or more instance masks.Type: ApplicationFiled: March 4, 2021Publication date: March 21, 2024Inventors: Jonathan Chung-Kuan Huang, Vighnesh Nandan Birodkar, Siyang Li, Zhichao Lu, Vivek Rathod
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Publication number: 20240098492Abstract: During operation, an access point may provide a first WLAN and a second WLAN, where the first WLAN uses a WPA2-compatible authentication protocol and the second WLAN uses a WPA3-compatible authentication protocol. In response to an association request or a probe request associated with (or from) an electronic device, the access point may establish a connection with the electronic device using the first WLAN. Then, the access point may confirm, with a computer system, that a binding between a passphrase associated with the electronic device and the second WLAN exists. Alternatively, when the binding does not exist, the access point may establish the binding in the computer system. Next, the access point may perform a BSS transition of the electronic device from the first WLAN to the second WLAN.Type: ApplicationFiled: September 6, 2023Publication date: March 21, 2024Applicant: ARRIS Enterprises LLCInventors: Wei-Sheng Hsu, Yu-Ting Chang, Weichih Huang, Kuan-Hsun Peng, Weiguo Xie, Christopher Mohammed, Shannon Moyes Clark, Siddhartha Datta, David Burns
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Patent number: 11935783Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.Type: GrantFiled: May 16, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
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Publication number: 20240088023Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Shao-Kuan LEE, Kuang-Wei YANG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
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Publication number: 20240076187Abstract: The present invention provides a preparation method of a battery composite material, wherein a precursor with the chemical formula FePO4 is formed by introducing air or oxygen during calcination. The precursor is then reacted with a first reactant containing lithium atoms and a carbon source to form a battery composite material with the chemical formula LiFePO4.Type: ApplicationFiled: August 29, 2023Publication date: March 7, 2024Inventors: KUAN-YIN FU, Jing-Xuan Wang, An-Feng Huang
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Publication number: 20240076105Abstract: A sunken-type cup lid, for covering on a cup mouth of a cup body, according to the present invention is disclosed herein, and comprises: a covering panel, a leaning-on portion and a camber-holding portion. On the covering panel, a sunken-type dome structure is formed to expand a contacting area, from the leaning-on portion laterally and tightly fitting against inside the cup body, to the camber-holding portion downwardly and tightly fitting overneath the cup mouth, so as to be in a multi-directional tight fit manner between the cup lid and the cup body. Thus, it can decrease a liquid-leakage probability incurred between the cup lid and the cup body, and an accidentally detaching probability of the cup lid away from the cup body.Type: ApplicationFiled: July 2, 2023Publication date: March 7, 2024Inventors: CHIEN-KUAN KUO, CHUN-HUANG HUANG
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Patent number: 11923243Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.Type: GrantFiled: August 30, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee, Shau-Lin Shue, Hsiao-Kang Chang
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Patent number: 11923358Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.Type: GrantFiled: July 28, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Pin Huang, Hou-Yu Chen, Chuan-Li Chen, Chih-Kuan Yu, Yao-Ling Huang
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Publication number: 20240071442Abstract: A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Chiao YEH, Chieh LEE, Chia-En HUANG, Ji Kuan LEE, Yao-Jen YANG
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Publication number: 20240073038Abstract: A certificate requesting method, a certificate issuing method, a certificate system and a computer-readable medium thereof are provided, in which subscriber identity identification information, a private key and a public key certificate bound to a first security chip are converted into a private key bound to a second security chip via an online identity authentication procedure, and the corresponding public key certificate is issued by a certificate authority server, so as to improve the usability, the convenience and the security thereof.Type: ApplicationFiled: August 30, 2023Publication date: February 29, 2024Inventors: Wen-Cheng WANG, Yao-Kuan HUANG, Wan-Ju YANG
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Publication number: 20240006571Abstract: A display panel includes a substrate, a plurality of LEDs, a planarization layer, and a patterned first conductive layer. The plurality of LEDs are on the substrate, each of the plurality of LEDs includes a first electrode facing a front side of the display panel. The planarization layer covers the plurality of LEDs. The first conductive layer is on the planarization layer. The planarization layer defines a plurality of holes, the electrode is exposed by a corresponding hole of the plurality of holes, and the first conductive layer electrical connects to the first electrode through the corresponding hole. The first conductive layer further comprises a trace portion and a plurality of reinforcing portions, each of the plurality of reinforcing portions is aligned with the corresponding hole and is attached to the trace portion. Methods of fabricating the display panel are further disclosed.Type: ApplicationFiled: June 19, 2023Publication date: January 4, 2024Applicant: Century Technology (Shenzhen) Corporation LimitedInventors: CHAN-KUAN HUANG, CHAO WU, DENG-KAI CHANG
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Patent number: 11853892Abstract: Example aspects of the present disclosure are directed to systems and methods that enable weakly-supervised learning of instance segmentation by applying a cut-and-paste technique to training of a generator model included in a generative adversarial network. In particular, the present disclosure provides a weakly-supervised approach to object instance segmentation. In some implementations, starting with known or predicted object bounding boxes, a generator model can learn to generate object masks by playing a game of cut-and-paste in an adversarial learning setup.Type: GrantFiled: July 10, 2019Date of Patent: December 26, 2023Assignee: GOOGLE LLCInventors: Matthew Alun Brown, Jonathan Chung-Kuan Huang, Tal Remez
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Publication number: 20220352430Abstract: An embodiment of the present invention provides a micro light emitting diode (LED) array and its manufacturing method. The micro-LED includes a substrate, an epitaxial layer formed on the substrate, and a conversion film formed on the epitaxial layer. Pixels can be defined through lithography, and the pixel size can be very small. This method is characterized in that a mass transfer is not required.Type: ApplicationFiled: July 13, 2022Publication date: November 3, 2022Inventors: Ching-Fuh Lin, Chun-Yu Lin, Yi-Shan Lin, Jung-Kuan Huang
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Patent number: 11430923Abstract: An embodiment of the present invention provides a micro light emitting diode (LED) array and its manufacturing method. The micro-LED includes a substrate, an epitaxial layer formed on the substrate, and a conversion film formed on the epitaxial layer. Pixels can be defined through lithography, and the pixel size can be very small. This method is characterized in that a mass transfer is not required.Type: GrantFiled: January 7, 2020Date of Patent: August 30, 2022Assignee: National Taiwan UniversityInventors: Ching-Fuh Lin, Chun-Yu Lin, Yi-Shan Lin, Jung-Kuan Huang
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Publication number: 20220209074Abstract: Embodiments of the present invention provide a light-emitting film, a light-emitting film array, a micro-light emitting diode (LED) array, and their manufacturing methods. In one embodiment, epitaxial layers are formed on a substrate, and a conversion film is formed on a corresponding epitaxial layer. Pixels can be defined through lithography with a very small pixel size. A mass transfer is unnecessary for this method. The produced light-emitting films and the conversion films are homogeneous films and are insoluble in water, and the manufacturing steps can be simplified due to the waterproofing function of the films.Type: ApplicationFiled: March 30, 2021Publication date: June 30, 2022Inventors: Ching-Fuh Lin, Jung-Kuan Huang, Teng-Yi Huang, Yi-Shan Lin, Han-Yu Tsai
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Publication number: 20210256707Abstract: Example aspects of the present disclosure are directed to systems and methods that enable weakly-supervised learning of instance segmentation by applying a cut-and-paste technique to training of a generator model included in a generative adversarial network. In particular, the present disclosure provides a weakly-supervised approach to object instance segmentation. In some implementations, starting with known or predicted object bounding boxes, a generator model can learn to generate object masks by playing a game of cut-and-paste in an adversarial learning setup.Type: ApplicationFiled: July 10, 2019Publication date: August 19, 2021Inventors: Matthew Alun Brown, Jonathan Chung-Kuan Huang, Tal Remez
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Patent number: D1022641Type: GrantFiled: October 19, 2022Date of Patent: April 16, 2024Assignee: Yeu Chyuan Industrial Co., Ltd.Inventor: Yung-Kuan Huang
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Patent number: D1024051Type: GrantFiled: August 10, 2021Date of Patent: April 23, 2024Assignee: Acer IncorporatedInventors: Hui-Jung Huang, Hong-Kuan Li, I-Lun Li, Ling-Mei Kuo, Kuan-Ju Chen, Fang-Ying Huang, Kai-Hung Huang, Szu-Wei Yang, Kai-Teng Cheng